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參數資料
| 型號： | ADF4116 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | PLL Frequency Synthesizer(PLL頻率合成器) |
| 中文描述： | 鎖相環頻率合成器（PLL頻率合成器） |
| 文件頁數： | 4/9頁 |
| 文件大小： | 77K |
| 代理商： | ADF4116 |
–4–
plane should be placed as close as possible to this pin. V
CC
2 must be the same value as V
CC
1.
Charge Pump Power Supply. T his should be greater than or equal to V
CC
.
TECHNCAL
Digital Power Supply. T his may range from 2.7V to 5.5V. Decoupling capacitors to the digital ground
Prelim D2 7/98
ADF4116/ADF4117/ADF4118
Prelimnary Technical Data
PIN C ONF IGUR A T ION
PIN D E SC R IPT ION
Mnemonic
Function
F L
O
Fast Lock Switch Output. T his can be used to switch an external resistor to change the loop filter band-
width. T his will speed up locking of the PLL.
Charge Pump Output. T his is normally connected to a loop filter which drives the input to an external
V C O.
Charge Pump Ground
Analog Ground
Complementary Input to the RF Prescaler. T his point should be decoupled to the ground plane with a
small bypass capacitor. If this is not done then there will be some degradation in RF sensitivity.
Input to the RF Prescaler. T his small signal input is normally taken from the VCO.
Analog Power Supply. T his may range from 2.7V to 5.5V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AV
DD
must be the same value as DV
DD
.
Reference Input. T his is a CMOS input with a nominal threshold of AV
DD
/2 and an equivalent input
resistance of 100k
.
T he oscillator input can be driven from a T T L or CMOS crystal oscillator.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. T aking the pin high will power up the device depending on the status of the power-
down bit F2.
Serial Clock Input. T his serial clock is used to clock in the serial data to the registers. T he data is
latched into the 21-bit shift register on the CLK rising edge. T his input is a high impedance CMOS
input.
Serial Data Input. T he serial data is loaded MSB first with the two LSBs being the control bits. T his
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches, the latch being selected using the control bits.
T his multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency
to be accessed externally.
C P
C PG N D
A G N D
RF
IN
B
RF
IN
A
AV
DD
REF
IN
D G N D
C E
C L K
D AT A
L E
M U X OU T
DV
DD
V
P
REF
IN
CLK
DATA
LE
MU XOU T
F L
O
RF
IN
A
CP
CPG ND
AG ND
RF
IN
B
V
CC
1
DG ND
CE
V
CC
2
V
P
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADF4116
ADF4117
ADF4118
相關PDF資料 |
PDF描述 |
|---|---|
| ADF4118 | RF PLL Frequency Synthesizers |
| ADF4117BCP | BATT LITHIUM COIN 3V 48MAH COIN-W/LEGS 12.5MM |
| ADF4117BRU | RF PLL Frequency Synthesizers |
| ADF4118BCP | RF PLL Frequency Synthesizers |
| ADF4118BRU | RF PLL Frequency Synthesizers |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADF4116_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4116BCP | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4116BRU | 功能描述:IC SYNTH PLL RF 550MHZ 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4116BRU-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 16-Pin TSSOP T/R 制造商:Analog Devices 功能描述:SINGLE INTEGER-N 550MHZ PLL |
| ADF4116BRU-REEL7 | 功能描述:IC PLL FREQ SYNTHESIZER 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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