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參數資料
| 型號： | ADF4116 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | PLL Frequency Synthesizer(PLL頻率合成器) |
| 中文描述： | 鎖相環頻率合成器（PLL頻率合成器） |
| 文件頁數： | 7/9頁 |
| 文件大?。?/td> | 77K |
| 代理商： | ADF4116 |
–7–
When the VCO characteristics are positive this should be
set to “1”. When they are negative it should be set to
“ 0” .
C harge Pump T hree-State
T his bit puts the charge pump into three-state mode when
programmed to a “1”. It should be set to “0” for normal
operation.
F astlock E nable Bit
DB9 of the Function Latch in the ADF4116 familiy is
the Fastlock Enable Bit. Only when this is “1” is
Fastlock enabled.
F astlock Mode Bit
DB11 of the Function Latch in the ADF4116 family is
the Fastlock Mode bit. When Fastlock is enabled, this bit
determines which Fastlock Mode is used. If the Fastlock
Mode bit is “0” then Fastlock Mode 1 is selected and if
the Fastlock Mode bit is “1”, then Fastlock Mode 2 is
selected.
If Fastlock is not enabled (DB9 = “0”), then DB11
(ADF4116) determines the state of the FL
O
output. FL
O
state will be the same as that programmed to DB11.
Fastlock Mode 1
In the ADF4116 family, the output level of FL
O
is pro-
grammed to a low state and the charge pump current is
switched to the high value (1mA). FL
O
is used to switch a
resistor in the loop filter and ensure stability while in
Fastlock by altering the loop bandwidth.
TECHNCAL
Prelimnary Technical Data
ADF4116/ADF4117/ADF4118
Prelim D2 7/98
All active DC current paths are removed.
T he R, N and timeout counters are forced to their load
state conditions.
T he charge pump is forced into three-state mode.
T he digital clock detect circuitry is reset.
T he RF
IN
input is debiased to a high impedance state.
T he oscillator input buffer circuitry is disabled.
T he input register remains active and capable of loading
and latching data.
MUX OUT C ontrol
T he on-chip multiplexer is controlled by F5, F4 and F3
on the an ADF4116 family.
Phase D etector Polarity
F6 in the ADF4116 sets the Phase Detector Polarity.
T he device enters Fastlock by having a “1” written to the
CP Gain bit in the N register. T he device exits Fastlock
by having a “0” written to the CP Gain bit in the N regis-
ter.
Fastlock Mode 2
In the ADF4116 family, the output level of FL
O
is pro-
grammed to a low state and the charge pump current is
switched to the high value (1mA). FL
O
is used to switch a
resistor in the loop filter and ensure stability while in
Fastlock by altering the loop bandwidth.
T he device enters Fastlock by having a “1” written to the
CP Gain bit in the N register. T he device exits Fastlock
under the control of the T imer Counter. After the
timeout period determined by the value in T C4 - T C1,
“0” and the device reverts to normal mode instead of
F astlock.
T imer C ounter C ontrol
In the ADF4116 family, the user has the option of switch-
ing between two charge pump current values to speed up
locking to a new frequency.
When using the Fastlock feature with the ADF4116 fam-
ily, the normal sequence of events is as follows:
T he user must make sure that Fastlock is enabled. Set
DB9 of the ADF4116 family to “1”. T he user must also
choose which Fastlock Mode to use. As discussed in the
previous section, Fastlock Mode 2 uses the values in the
T imer Counter to determine the timeout period before
reverting to normal mode operation after Fastlock.
Fastlock Mode 2 is chosen by setting DB11 of the
ADF4116 family to “1”.
T he user must also decide how long they want the high
current (1mA) to stay active before reverting to low cur-
rent (210uA). T his is controlled by the T imer Counter
Control Bits DB14 to DB11 (T C4 - T C1) in the Func-
tion Latch. T he truth table is given in T able 11.
Now, when the user wishes to program a new output fre-
quency, they can simply program the A,B counter latch
with new values for A and B. At the same time they can
set the CP Gain bit to a “1” ,which sets the charge pump
1mA for a period of time determined by T C4 - T C1.
When this time is up, the charge pump current reverts to
210uA. At the same time the CP Gain Bit in the A, B
Counter latch is reset to 0 and is now ready for the next
time that the user wishes to change the frequency again.
F5
0
0
0
0
1
1
1
1
F4
0
0
1
1
0
0
1
1
F3
0
1
0
1
0
1
0
1
Output
Three-State Output
Digital Lock Detect
N Divider Output
Active High
R Divider Output
N-Channel Open Drain Lock Detect
Serial Data Output
Active Low
T able 10. MUX OUT T ruth T able
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| ADF4116_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
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| ADF4116BRU | 功能描述:IC SYNTH PLL RF 550MHZ 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4116BRU-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 16-Pin TSSOP T/R 制造商:Analog Devices 功能描述:SINGLE INTEGER-N 550MHZ PLL |
| ADF4116BRU-REEL7 | 功能描述:IC PLL FREQ SYNTHESIZER 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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