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參數資料
| 型號： | ADF4116 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | PLL Frequency Synthesizer(PLL頻率合成器) |
| 中文描述： | 鎖相環頻率合成器（PLL頻率合成器） |
| 文件頁數： | 6/9頁 |
| 文件大小： | 77K |
| 代理商： | ADF4116 |
–6–
DATA
F9
F10
F11
F12
F13
F14
TECHNCAL
DB14 DB13
DB12
DB11
DB10 DB9
Prelim D2 7/98
ADF4116/ADF4117/ADF4118
Prelimnary Technical Data
T able 7. B Counter Divide Ratio
Divide Ratio
3
4
*
*
8191
NOT ES
1.Divide ratios less than 3 are prohibited.
2.Divide ratio: 3 to 8191.
3.B must be greater than or equal to A.
B13
0
0
*
*
1
B12
0
0
*
*
1
B11
0
0
*
*
1
B10
0
0
*
*
1
B9
0
0
*
*
1
B8
0
0
*
*
1
B7
0
0
*
*
1
B6
0
0
*
*
1
B5
0
0
*
*
1
B4
0
0
*
*
1
B3
0
1
*
*
1
B2
1
0
*
*
1
B1
1
0
*
*
1
Pulse Swallow F unction
T he A and B counters, in conjunction with the dual modu-
lus prescaler make it possible to generate output frequen-
cies which are spaced only by the Reference Frequency
divided by R . T he equation for the VCO frequency is as
follows:
f
VCO
= [(P x B) + A] x f
REFIN
/R
f
VCO
:
Ouput Frequency of external voltage
controlled oscillator (VC O).
P:
B:
Preset modulus of dual modulus prescaler.
Preset Divide Ratio of binary 13-bit counter (3
to 8191).
Preset Divide Ratio of binary 5-bit swallow
counter.
f
REFIN
: Ouput frequency of the external reference
frequency.
R :
Preset divide ratio of binary 14-bit
programmable reference counter (3 to 16383).
A :
F unction L atch
With C2, C1 set to 1,0, the on-chip function latch will be
programmed. T able 8 shows the input data format for
programming the Function L atch.
T able 8. Programming the Function Latch
DB20
DB19
DB18 DB17 DB16 DB15
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2(1)
C1(0)
F1
F2
F3
F4
F5
F7
F8
F15
F16
F17
F18
F19
F6
Control
Bits
C
R
P
D
MUXOUT
Control
P
P
C
3
P
D
F
E
F
M
Timer Counter
Control
C ounter R eset
DB2 is the counter reset bit for the ADF4116 family .
When this is “1”, the R counter and the A,B counters are
reset. For normal operation this bit should be “0”.
Upon
powering up, the F1 bit needs to be disabled, the N counter resumes
counting in “close” alignment with the R counter. (The maximum error
is one prescaler cycle)
.
Power D own
F2 and F18 on the ADF4116, provide programmable
power-down modes. T hey are enabled by the CE pin.
When the CE pin is low, the device is immediately dis-
abled regardless of the states of PD2, PD1.
CE Pin
PD2
PD1
Mode
0
1
1
1
X
X
0
1
X
0
1
1
Asynchronous Power-Down
Normal Operation
Asynchronous Power-Down
Synchronous Power-Down
In the programmed asynchronous power-down, the device
powers down immediately after latching a “1” into bit
PD1, with the condition that PD2 has been loaded with a
“ 0” .
In the programmed synchronous power-down, the device
power down is gated by the charge pump to prevent un-
wanted frequency jumps. Once the power-down is enabled
by writing a “1” into bit PD1 (on condition that a “1” has
also been loaded to PD2), then the device will go into
power-down after the first successive charge pump event.
When a power down is activated (either synchronous or
asynchronous mode including CE-pin-activated power
down), the following events occur:
T able 9. Power Down T ruth T able
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