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參數資料
| 型號： | ADF4116 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | PLL Frequency Synthesizer(PLL頻率合成器) |
| 中文描述： | 鎖相環頻率合成器（PLL頻率合成器） |
| 文件頁數： | 8/9頁 |
| 文件大小： | 77K |
| 代理商： | ADF4116 |
–8–
PRELMNARY
DATA
TECHNCAL
there is another initialisation.
T he CE pin Method.
Apply Vcc.
Bring CE low to put the device into power-down. T his is
an asychronous power-down in that it happens immedi-
ately.
Program the Function Latch (10).
Program the R Counter Latch (00).
Program the N Counter Latch (01).
Bring CE high to take the device out of power-down.
T he R and N counter will now resume counting in close
alignment.
Note that after CE goes high, a duration of 1us may be
required for the prescaler bandgap voltage and oscillator
input buffer bias to reach steady state.
CE can be used to power the device up and down in order
to check for channel activity. T he input register does not
need to be reprogrammed each time the device is disabled
and enabled as long as it has been programmed at least
once after V
DD
was initially applied.
Prelim D2 7/98
ADF4116/ADF4117/ADF4118
Prelimnary Technical Data
TC4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TC3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TC2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TC1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Timeout (PD Clock Cycles)
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
C harge Pump C urrents
In the ADF4116, when Fastlock is not enabled (F8 = “0”
in the Function Latch) the CP Gain bit will switch the
charge pump current between two values. With CP Gain
bit = “0”, the current is 210uA, and with the GO bit =
“1”, the current is 1mA.
T he Initialisation L atch
When C2, C1 = 1, 1 then the Initialisation Latch is pro-
grammed. T his is essentially the same as the Function
Latch (programmed when C2, C1 = 1, 0).
However, when the Initialisation Latch is programmed
there is a additional internal reset pulse applied to the R
and N counters. T his pulse ensures that the N counter is
at load point when the N counter data is latched and the
device will begin counting in close phase alignment.
If the Latch is programmed for synchronous powerdown
(CE is High; F2 is High; F18 is Low), the internal pulse
also triggers this powerdown. T he prescaler reference and
the oscillator input buffer are unaffected by the internal
reset pulse and so close phase alignment is maintained
when counting resumes.
When the first N counter data is latched after
initialisation, the internal reset pulse is again activated.
However, successive N counter loads after this will not
trigger the internal reset pulse.
D evice Programming After Initial Power-Up.
After initially powering up the device, there are three ways
to program the device.
Initialisation L atch Method.
Apply Vcc.
Program the Initialisation Latch (“11” in 2 lsb’s of input
word). Make sure that F1bit is programmed to “0”.
T hen do an R load (“00” in 2 lsb’s).
T hen do an N load (“01” in 2 lsb’s).
When the Initialisation Latch is loaded, the following
occurs:
T able 11. T imer Counter Values
1. T he function latch contents are loaded.
to load state conditions and also tri-states the charge
pump. Note that the prescaler bandgpap reference and
the oscillator input buffer are unaffected by the internal
reset pulse, allowing close phase alignment when counting
resumes.
3. Latching the first N counter data after the initialisation
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