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參數資料
| 型號： | ADF4207BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Dual RF PLL Frequency Synthesizers |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數： | 10/20頁 |
| 文件大小： | 206K |
| 代理商： | ADF4207BRU |
REV. 0
ADF4206/ADF4207/ADF4208
–10–
DELAY
ELEMENT
U3
CLR2
Q2
D2
U2
CLR1
Q1
D1
CHARGE
PUMP
DOWN
UP
HI
HI
U1
R DIVIDER
N DIVIDER
CP OUTPUT
R DIVIDER
N DIVIDER
CP
CPGND
V
P
Figure 5. PFD Simplified Schematic and Timing (In Lock)
The PFD includes a delay element which sets the width of the
antibacklash phase. The typical value for this is in the ADF4206
family is 3 ns. The pulse ensures that there is no deadzone in
the PFD transfer function and minimizes phase noise and refer-
ence spurs.
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4206 family allows the
user to access various internal points on the chip. The state
of MUXOUT is controlled by P3, P4, P11, and P12. See
Tables III and V. Figure 6 shows the MUXOUT section in
block diagram form.
CONTROL
MUX
DV
DD
MUXOUT
DGND
RF2 ANALOG LOCK DETECT
RF2 R COUNTER OUTPUT
RF2 N COUNTER OUTPUT
RF2/RF1 ANALOG LOCK DETECT
RF1 R COUNTER OUTPUT
RF1 N COUNTER OUTPUT
RF1 ANALOG LOCK DETECT
Figure 6. MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for analog lock detect. The
N-channel open-drain analog lock detect should be operated
with an external pull-up resistor of 10 k
nominal. When lock
has been detected it is high with narrow low-going pulses.
INPUT SHIFT REGISTER
The functional block diagram for the ADF4206 family is shown
on Page 1. The main blocks include a 22-bit input shift register,
a 14-bit R counter, and an 17-bit N counter, comprising a 6-bit
A counter and an 11-bit B counter. Data is clocked into the 22-bit
shift register on each rising edge of CLK. The data is clocked
in MSB first. Data is transferred from the shift register to one of
four latches on the rising edge of LE. The destination latch is
determined by the state of the two control bits (C2, C1) in the
shift register. These are the two LSBs DB1, DB0, as shown in
the timing diagram of Figure 1. The truth table for these bits is
shown in Table I.
Table I. C2, C1 Truth Table
Control Bits
C2
C1
Data Latch
0
0
1
1
0
1
0
1
RF2 R Counter
RF2 AB Counter (and Prescaler Select)
RF1 R Counter
RF1 AB Counter (and Prescaler Select)
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PDF描述 |
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| ADF4208BRU | Dual RF PLL Frequency Synthesizers |
| ADF4206 | Dual RF PLL Frequency Synthesizers |
| ADF4206BRU | Dual RF PLL Frequency Synthesizers |
| ADF4212 | Dual RF/IF PLL Frequency Synthesizers |
| ADF4210 | Dual RF/IF PLL Frequency Synthesizers |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADF4208 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual RF PLL Frequency Synthesizers |
| ADF4208BRU | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 20-Pin TSSOP |
| ADF4208BRU-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 20-Pin TSSOP T/R |
| ADF4208BRU-REEL7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 20-Pin TSSOP T/R |
| ADF4208BRUZ | 功能描述:IC PLL FREQ SYNTHESIZER 20TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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