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參數資料
| 型號： | ADF4207BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Dual RF PLL Frequency Synthesizers |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數： | 17/20頁 |
| 文件大?。?/td> | 206K |
| 代理商： | ADF4207BRU |
REV. 0
ADF4206/ADF4207/ADF4208
–17–
RF SECTION (RF1)
Programmable RF1 Reference (R) Counter
If control bits (C2, C1) are (1, 0), the data is transferred from
the input shift register to the 14 Bit RF1 R counter. Table V
shows the input shift register data format for the RF1 R counter
and the divide ratios possible.
RF1 Phase Detector Polarity
P9 sets the RF1 Phase Detector Polarity. When the RF1 VCO
characteristics are positive this should be set to “1.” When they
are negative it should be set to “0.” See Table V.
RF1 Charge Pump Three-State
P10 puts the RF1 charge pump into three-state mode when
programmed to a “1.” It should be set to “0” for normal opera-
tion. See Table V.
RF1 Program Modes
Table III and Table V show how to set up the Program Modes
in the ADF420x family.
RF1 Charge Pump Currents
Replaced with a P13 programs the current setting for the RF1
charge pump. See Table V.
Programmable RF1 AB Counter
If control bits (C2, C1) are (1, 1), then the data in the input
register is used to program the RF1 AB counter. The AB
counter consists of a 6-bit swallow counter (A counter) and
11-bit programmable counter (B counter). Table VI shows
the input register data format for programming the RF1 AB
counter and the divide ratios possible. See Table VI.
RF1 Prescaler Value
P14 in the RF1 A, B counter latch set the RF1 prescaler value.
See Table VI.
RF1 Power-Down
Setting P16 in the RF1 AB counter high powers down RF1 side.
RF Fastlock
The fastlock feature can improve the lock time of the PLL. It
increases charge pump current to a maximum for a period of
time. Fastlock of the ADF420x family is activated by setting
P13 in the reference counter high and setting the fastlock switch
on using MUXOUT. Switching in an external resistor using
MUXOUT compensates the loop dynamics for the effect of
increasing charge pump current. Setting P13 low removes the
PLL from fastlock mode.
OSC
OUT
MUXOUT
ADF4207
V
P
2
CP
RF2
V
DD
2 V
DD
1
V
P
1
CP
RF1
RF2
IN
RF1
IN
OSC
IN
CLK
DATA
LE
D
R
D
R
A
R
A
R
DECOUPLING CAPACITORS (22 F/10pF) ON V
, V
OF
THE ADF4207, AND ON V
OF THE VCOs HAVE BEEN
OMITTED FROM THE DIAGRAM TO AID CLARITY.
VCO190-125T
V
CC
V
CC
S
100pF
18
18
18
100pF
IF
OUT
100pF
51
30pF
10MHz
18k
1.3nF
13nF
2.7k
620pF
3.3k
V
P
V
DD
V
P
100pF
18
RF
OUT
100pF18
18
100pF
51
LOCK DETECT
30pF
VCO190-1068U
Figure 7. GSM Handset Receiver Local Oscillator Using the ADF4207
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| ADF4208BRU | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 20-Pin TSSOP |
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| ADF4208BRUZ | 功能描述:IC PLL FREQ SYNTHESIZER 20TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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