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參數資料
| 型號： | ADF4207BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Dual RF PLL Frequency Synthesizers |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數： | 19/20頁 |
| 文件大小： | 206K |
| 代理商： | ADF4207BRU |
REV. 0
ADF4206/ADF4207/ADF4208
–19–
INTERFACING
The ADF4206/ADF4207/ADF4208 family has a simple SPI-
compatible serial interface for writing to the device. SCLK,
SDATA, and LE (Latch Enable) control the data transfer. When
LE goes high, the 22 bits that have been clocked into the input
register on each rising edge of SCLK will be transferred to the
appropriate latch. See Figure 1 for the Timing Diagram and
Table I for the Latch Truth Table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device is
909 kHz or one update every 1.1 ms. This is certainly more than
adequate for systems that will have typical lock times in hun-
dreds of microseconds.
ADuC812 Interface
Figure 10 shows the interface between the ADF420x family and
the ADuC812 microconverter. Since the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI Master
Mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF420x family
needs a 22-bit word. This is accomplished by writing three 8-bit
bytes from the microconverter to the device. When the third
byte has been written, the LE input should be brought high to
complete the transfer.
On first applying power to the ADF420x family, it requires four
writes (one each to the R counter latch and the AB counter latch
for both RF1 and RF2 side) for the output to become active.
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed will be about
180 kHz.
SCLOCK
MOSI
I/O PORTS
ADuC812
SCLK
SDATA
LE
MUXOUT
(LOCK DETECT)
ADF4206/
ADF4207/
ADF4208
Figure 9. ADuC812 to ADF420x Family Interface
ADSP-2181 Interface
Figure 10 shows the interface between the ADF420x family and
the ADSP-21xx Digital Signal Processor. As previously noted,
the ADF420x family needs a 22-bit serial word for each latch
write. The easiest way to accomplish this using the ADSP21-xx
family is to use the Autobuffered Transmit Mode of operation
with Alternate Framing. This provides a means for transmitting
an entire block of serial data before an interrupt is generated.
Set up the word length for eight bits and use three memory
locations for each 22-bit word. To program each 22-bit latch,
store the three 8-bit bytes, enable the Autobuffered mode and
then write to the transmit register of the DSP. This last opera-
tion initiates the autobuffer transfer.
SCLOCK
DT
I/O FLAG
ADSP-21xx
SCLK
SDATA
LE
MUXOUT
(LOCK DETECT)
ADF4206/
ADF4207/
ADF4208
TFS
Figure 10. ADSP-21xx to ADF420x Family Interface
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADF4208 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual RF PLL Frequency Synthesizers |
| ADF4208BRU | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 20-Pin TSSOP |
| ADF4208BRU-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 20-Pin TSSOP T/R |
| ADF4208BRU-REEL7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 20-Pin TSSOP T/R |
| ADF4208BRUZ | 功能描述:IC PLL FREQ SYNTHESIZER 20TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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