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參數資料
| 型號： | ADF4207BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Dual RF PLL Frequency Synthesizers |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數： | 16/20頁 |
| 文件大小： | 206K |
| 代理商： | ADF4207BRU |
REV. 0
ADF4206/ADF4207/ADF4208
–16–
PROGRAM MODES
Table III and Table V show how to set up the Program Modes
in the ADF420x family. The following should be noted:
1. RF2 and RF1 Analog Lock Detect indicate when the PLL
is in lock. When the loop is locked and either RF2 or RF1
Analog Lock Detect is selected, the MUXOUT pin will show a
logic high with narrow low-going pulses. When the RF2/RF1
Analog Lock Detect is chosen, the locked condition is indi-
cated only when both RF2 and RF1 loops are locked.
2. The RF2 Counter Reset mode resets the R and AB counters
in the RF2 section and also puts the RF2 charge pump into
three-state. The RF1 Counter Reset mode resets the R and AB
counters in the RF1 section and also puts the RF1 charge
pump into three-state. The RF2 and RF1 Counter Reset
mode does both of the above.
Upon removal of the reset bits, the AB counter resumes count-
ing in close alignment with the R counter (maximum error is
one prescaler output cycle).
3. The Fastlock mode uses MUXOUT to switch a second loop
filter damping resistor to ground during Fastlock operation.
Activation of Fastlock occurs whenever RF1 CP Gain in the
RF1 Reference counter is set to one.
POWER-DOWN
It is possible to program the ADF420x family for either syn-
chronous or asynchronous power-down on either the RF2 or
RF1 side.
Synchronous RF2 Power-Down
Programming a “1” to P7 of the ADF420x family will initiate a
power-down. If P2 of the ADF420x family has been set to “0”
(normal operation), a synchronous power-down is conducted.
The device will automatically put the charge pump into three-
state and then complete the power-down.
Asynchronous RF2 Power-Down
If P2 of the ADF420x family has been set to “1” (three-state
the RF2 charge pump), and P7 is subsequently set to “1,” an
asynchronous power-down is conducted. The device will go into
power-down on the rising edge of LE, which latches the “1” to
the RF2 power-down bit (P7).
Synchronous RF1 Power-Down
Programming a “1” to P16 of the ADF420x family will initiate
a power-down. If P10 of the ADF420x family has been set to
“0” (normal operation), a synchronous power-down is conducted.
The device will automatically put the charge pump into three-
state and then complete the power-down.
Asynchronous RF1 Power-Down
If P10 of the ADF420x family has been set to “1” (three-state
the RF1 charge pump), and P16 is subsequently set to “1,” an
asynchronous power-down is conducted. The device will go into
power-down on the rising edge of LE, which latches the “1” to
the RF1 power-down bit (P16).
Activation of either synchronous or asynchronous power-down
forces the RF2/RF1 loop’s R and N dividers to their load
state conditions and the RF2/RF1 input section is debiased to
a high impedance state.
The reference oscillator circuit is only disabled if both the RF2
and RF1 power-downs are set.
The input register and latches remain active and are capable of
loading and latching data during all the power-down modes.
The RF2/RF1 section of the devices will return to normal pow-
ered up operation immediately upon LE latching a “0” to the
appropriate power-down bit.
IF SECTION (RF2)
Programmable RF2 Reference (R) Counter
If control bits (C2, C1) are (0, 0), the data is transferred from
the input shift register to the 14-bit RF2 R counter. Table III
shows the input shift register data format for the RF2 R counter
and the divide ratios possible.
RF2 Phase Detector Polarity
P1 sets the RF2 Phase Detector Polarity. When the RF2 VCO
characteristics are positive, this should be set to “1.” When they
are negative, it should be set to “0.” See Table III.
RF2 Charge Pump Three-State
P2 puts the RF2 charge pump into three-state mode when pro-
grammed to a “1.” It should be set to “0” for normal operation.
See Table III.
RF2 Program Modes
Table III and Table V show how to set up the Program Modes
in the ADF420x family.
RF2 Charge Pump Currents
Bit P5 programs the current setting for the RF2 charge pump.
See Table III.
Programmable RF2 AB Counter
If control bits (C2, C1) are (0, 1), the data in the input register is
used to program the RF2 AB counter. The AB counter consists of
a 6-bit swallow counter (A counter) and 11-bit programmable
counter (B counter). Table IV shows the input register data
format for programming the RF2 AB counter and the divide
ratios possible.
RF2 Prescaler Value
P6 in the RF2 AB counter latch sets the RF2 prescaler value. See
Table IV.
RF2 Power-Down
P7 in Table IV is the power-down bit for the RF2 side.
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| ADF4208BRUZ | 功能描述:IC PLL FREQ SYNTHESIZER 20TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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