
REV. 0
–26–
ADF4251
IF
OUT
J6
C15
100pF
R12
18
R13
18
R14
18
C16
100pF
VCO2
RF
OUT
VCC
V
IN
10
14
2
C4
10pF
C3
22 F
6.3V
R48
0
VVCO
R17
13k
C20
82pF
C19
2.2nF
C18
270pF
R16
7.5k
R15
51
C17
100pF
C10
10pF
C9
22 F
6.3V
R44
0
V
P
C6
10pF
C5
22 F
6.3V
C8
10pF
C7
22 F
6.3V
V
D
1
V
D
2
V
D
3
D
D
V
P
2
CP
IF
IF
IN
A
R43
0
R1
20
VDD
’
V
DD
RF
OUT
J7
C27
100pF
R22
18
R21
18
R23
18
C26
100pF
VCO1
RF
OUT
VCC
V
IN
10
14
2
C30
10pF
C29
22 F
6.3V
R49
0
VVCO
R20
470
C25
3.3nF
C24
100nF
C23
10nF
R19
270
R24
51
C28
100pF
C12
10pF
C11
22 F
6.3V
V
P
V
P
1
CP
RF
RF
IN
A
C44
100pF
CP
GND
1
RF
IN
B
A
GND
1
D
GND
A
GND
2
CP
GND
2
MUXOUT
R27
10k
T16
R28
10k
R29
10k
D4
V
DD
CLK
C43
100pF
R27
2.7k
DATA
LE
T14
R11
51
C14
1nF
C13
1nF
REF
IN
J5
T13
R47
0
Y3
B+
O/P
4
3
2
GND
C45
10pF
C46
22 F
R46
0
R45
0
3V
5V
U1
ADF4251BCP
VCO190–540T
VCO190–1730T
Figure 11. Typical PLL Circuit Schematic
ADSP-21xx
ADF4251
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
SCLK
DT
I/O FLAGS
TFS
Figure 10. ADSP-21xx to ADF4251 Interface
ADSP-2181 Interface
Figure 10 shows the interface between the ADF4251 and the
ADSP-21xx digital signal processor. Each latch of the ADF4251
needs (at most) a 24-bit word. The easiest way to accomplish this
using the ADSP-21xx family is to use the autobuffered transmit
mode of operation with alternate framing. This provides a means
for transmitting an entire block of serial data before an interrupt is
generated. Set up the word length for eight bits and use three memory
locations for each 24-bit word. To program each 24-bit latch, store
the three 8-bit bytes, enable the autobuffered mode, and then write
to the transmit register of the DSP. This last operation initiates the
autobuffer transfer.
Powerdown Circuit
The attached circuit in Figure 10 shows how to shut down the
ADF4251 and the accompanying RF and IF VCO. The
ADG701 switch goes closed circuit when a Logic High is applied
to the IN input. The low cost switch is available in SOT-23 and
SOIC packages.
PCB DESIGN GUIDELINES FOR CHIP-SCALE
PACKAGE
The leads on the chip-scale package (CP-24) are rectangular. The
printed circuit board pad for these should be 0.1 mm longer than
the package land length and 0.05 mm wider than the package land
width. The land should be centered on the pad. This will ensure
that the solder joint size is maximized.
The bottom of the chip-scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern. This will ensure that
shorting is avoided.
Thermal vias may be used on the printed circuit board thermal pad
to improve thermal performance of the package. If vias are used,
they should be incorporated in the thermal pad at 1.2 mm pitch
grid. The via diameter should be between 0.3 mm and 0.33 mm,
and the via barrel should be plated with 1 oz copper to plug the via.