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參數資料
| 型號： | ADF4360-7BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Integrated Synthesizer and VCO |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, QCC24 |
| 封裝： | 4 X 4 MM, MO-220-VGGD-2, LFCSP-24 |
| 文件頁數： | 14/20頁 |
| 文件大?。?/td> | 336K |
| 代理商： | ADF4360-7BCP |
PRELIMINARY TECHNICAL DATA
REV. PrA 07/03
–14–
0
P
ADF4360-2
CONTROL LATCH
With (C2, C1) = (0,0), the Control Latch is programmed. Table III
shows the input data format for programming the Control latch.
Prescaler Value
In the ADF4360 family, P2 and P1 in the Control Latch set the
Prescaler values.
Power-Down
DB21 (PD2) and DB20 (PD1) provide programmable power-
down modes.
In the programmed asynchronous power-down, the device
powers down immediately after latching a “1” into bit PD1,
with the condition that PD2 has been loaded with a “0”.
In the programmed synchronous power-down, the device
power down is gated by the charge pump to prevent
unwanted frequency jumps. Once the power-down is enabled
by writing a “1” into bit PD1 (on condition that a “1” has also
been loaded to PD2), then the device will go into power-down
on the second rising edge of the R counter output, after LE
goes high.
When the CE pin is low, the device is immediately disabled
regardless of the states of PD1 or PD2.
When a power down is activated (either synchronous or
asynchronous mode), the following events occur:
All active DC current paths are removed.
The R, N and timeout counters are forced to their load state
conditions.
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RF outputs are debiased to a high impedance state.
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading and
latching data.
Charge Pump Currents
CPI3, CPI2, CPI1 in the ADF4360 family determine Current Setting 1.
CPI6, CPI5, CPI4 determine Current Setting 2. The truth table is
given in Table III.
Output Power Level
Bits PL1 & PL2 set the output power level of the VCO. The truth
table is given in Table III.
Mute Till Lock Detect
DB11 of the Control Latch in the ADF4360 family is the Mute Till
Lock Detect Bit. This function, when enabled, ensures that the RF
outputs are not switched on until the PLL has achieved lock.
CP Gain Bit
DB10 of the Control Latch in the ADF4360 family is the Charge
Pump Gain bit. When this is programmed to a “1” then Current
Setting 2 is used. When programmed to a “0”, Current Setting 1 is
used.
Charge Pump Three-State
This bit puts the charge pump into three-state mode when
programmed to a “1”. It should be set to “0” for normal operation.
Phase Detector Polarity
The PDP bit in the ADF4360 family sets the Phase Detector
Polarity. The positive setting enabled by programming a “1” is
used when using the on-chip VCO with a passive loop filter or with
an active non-inverting filter. It can also be set to “0”. This is
required if an active inverting loop filter is used.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, M1. Table 3 shows the
truth table.
Counter Reset
DB4 is the counter reset bit for the ADF4360 family. When this is “1”,
the R counter and the A,B counters are reset. For normal operation this
bit should be “0”.
Core Power Level
PC1 and PC2 set the power level in the VCO core. The recommended
setting is 15mA. The truth table is given in Table III.
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| ADF4360-7BCPZ | 功能描述:IC SYNTHESIZER/VCO 24-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
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