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參數(shù)資料
| 型號： | ADF7020 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Performance ISM Band FSK/ASK Transceiver IC |
| 中文描述： | 高性能ISM頻段FSK信號/賣出收發(fā)芯片 |
| 文件頁數(shù)： | 18/40頁 |
| 文件大小： | 797K |
| 代理商： | ADF7020 |
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ADF7020
Preliminary Technical Data
Postdemodulator Filter
A second-order, digital low-pass filter removes excess noise
from the demodulated bit stream at the output of the
discriminator. The bandwidth of this postdemodulator filter is
programmable and must be optimized for the user’s data rate. If
the bandwidth is set too narrow, performance is degraded due
to intersymbol interference (ISI). If the bandwidth is set too
wide, excess noise degrades the receiver’s performance.
Typically, the 3 dB bandwidth of this filter is set at
approximately 0.75 times the user’s data rate, using Bits
R4_DB(6:15).
Bit Slicer
The received data is recovered by threshold detecting the output
of the postdemodulator low-pass filter. In the correlator/
demodulator, the binary output signal levels of the frequency
discriminator are always centered on zero. Therefore, the slicer
threshold level can be fixed at zero and the demodulator
performance is independent of the run-length constraints of the
transmit data bit stream. This results in robust data recovery,
which does not suffer from the classic baseline wander
problems that exist in the more traditional FSK demodulators.
Rev. PrH | Page 18 of 40
Frequency errors are removed by an internal AFC loop that
measures the average IF frequency at the limiter output and
applies a frequency correction value to the fractional-N
synthesizer. This loop should be activated when the frequency
errors are greater than approximately 40% of the transmit
frequency deviation (see the AFC Section).
Data Synchronizer
An oversampled digital PLL is used to resynchronize the
received bit stream to a local clock. The oversampled clock rate
of the PLL (CDR_CLK) must be set at 32 times the data rate.
See the notes for the Register 3—Receiver Clock Register
section for a definition of how to program. The clock recovery
PLL can accommodate frequency errors of up to ±2%.
FSK Correlator Register Settings
To enable the FSK correlator/demodulator, Bits R4_DB(5:4)
should be set to [01]. To achieve best performance, the
bandwidth of the FSK correlator must be optimized for the
specific deviation frequency that is used by the FSK transmitter.
The discriminator BW is controlled in Register 6 by
R6_DB(4:13) and is defined as
)
10
800
/(
)
_
(
_
3
×
×
=
K
CLK
DEMOD
BW
tor
Discrimina
where:
DEMOD_CLK
is as defined in the Register 3—Receiver Clock
Register section, Note 2.
K
=
Round
(200e3/
FSK Deviation
)
To optimize the coefficients of the FSK correlator, two
additional bits, R6_DB14 and R6_DB29, must be assigned. The
value of these bits depends on whether
K
(as defined above) is
odd or even. These bits are assigned according to Table 7 and
Table 8.
Table 7. When K Is Even
K
K/2
Even
Even
Even
Odd
Table 8. When K Is Odd
K
(K + 1)/2
Odd
Even
Odd
Odd
Postdemodulator Bandwidth Register Settings
The 3 dB bandwidth of the postdemodulator filter is controlled
by Bits R4_ DB(6:15) and is given by
R6_DB14
0
0
R6_DB29
0
1
R6_DB14
1
1
R6_DB29
0
1
CLK
DEMOD
F
BWSetting
Demod
Post
CUTOFF
_
2
2
_
_
10
×
π
×
=
where
F
CUTOFF
is the target 3 dB bandwidth in Hz of the
postdemodulator filter. This should typically be set to 0.75 times
the data rate (DR).
Some sample settings for the FSK correlator/demodulator are
DEMOD_CLK
= 5 MHz
DR
= 9.6 kbps
F
DEV
= 20 kHz
Therefore,
F
CUTOFF
= 0.75 × 9.6 × 10
3
Hz
Post_Demod_BW
= 2
11
π
7.2 × 10
3
Hz/(5 MHz)
Post_Demod_BW
=
Round
(9.26) = 9
and
K
=
Round
(200 kHz)/20 kHz) = 10
Discriminator_BW
= (5 MHz × 10)/(800 × 10
3
) = 62.5 =
63 (rounded to nearest integer)
Table 9.
Setting Name
Post_Demod_BW
Discriminator BW
Dot Product
Rx Data Invert
Register Address
R4_DB(6:15)
R6_DB(4:13)
R6_DB14
R6_DB29
Value
0x09
0x3F
0
0
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| ADF7020-1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance FSK/ASK Transceiver IC |
| ADF7020-1BCPZ | 功能描述:IC TX FSK/ASK ISM BAND 48LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:30 系列:- 頻率:4.9GHz ~ 5.9GHz 數(shù)據(jù)傳輸率 - 最大:54Mbps 調(diào)制或協(xié)議:* 應(yīng)用:* 功率 - 輸出:-3dBm 靈敏度:- 電源電壓:2.7 V ~ 3.6 V 電流 - 接收:* 電流 - 傳輸:* 數(shù)據(jù)接口:PCB，表面貼裝 存儲容量:- 天線連接器:PCB，表面貼裝 工作溫度:-25°C ~ 85°C 封裝/外殼:68-TQFN 裸露焊盤 包裝:管件 |
| ADF7020-1BCPZ-RL | 功能描述:IC TX FSK/ASK ISM BAND 48-LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:30 系列:- 頻率:4.9GHz ~ 5.9GHz 數(shù)據(jù)傳輸率 - 最大:54Mbps 調(diào)制或協(xié)議:* 應(yīng)用:* 功率 - 輸出:-3dBm 靈敏度:- 電源電壓:2.7 V ~ 3.6 V 電流 - 接收:* 電流 - 傳輸:* 數(shù)據(jù)接口:PCB，表面貼裝 存儲容量:- 天線連接器:PCB，表面貼裝 工作溫度:-25°C ~ 85°C 封裝/外殼:68-TQFN 裸露焊盤 包裝:管件 |
| ADF7020-1BCPZ-RL7 | 功能描述:IC TX FSK/ASK ISM BAND 48-LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:30 系列:- 頻率:4.9GHz ~ 5.9GHz 數(shù)據(jù)傳輸率 - 最大:54Mbps 調(diào)制或協(xié)議:* 應(yīng)用:* 功率 - 輸出:-3dBm 靈敏度:- 電源電壓:2.7 V ~ 3.6 V 電流 - 接收:* 電流 - 傳輸:* 數(shù)據(jù)接口:PCB，表面貼裝 存儲容量:- 天線連接器:PCB，表面貼裝 工作溫度:-25°C ~ 85°C 封裝/外殼:68-TQFN 裸露焊盤 包裝:管件 |
| ADF7020BCP | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance ISM Band FSK/ASK Transceiver IC |
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