
ADF7020
Preliminary Technical Data
SERIAL INTERFACE
The serial interface allows the user to program the eleven 32-bit
registers using a 3-wire interface (SCLK, SDATA, and SLE). It
consists of a level shifter, 32-bit shift register and eleven latches.
Signals should be CMOS compatible. The serial interface is
powered by the regulator, and, therefore, is inactive when CE is
low.
Rev. PrH | Page 24 of 40
Data is clocked into the register, MSB first, on the rising edge of
each clock (SCLK). Data is transferred to one of eleven latches
on the rising edge of SLE. The destination latch is determined
by the value of the four control bits (C4 to C1). These are the
bottom four LSBs, DB3 to DB0, as shown in the timing diagram
in Figure 2. Data can also be read back on the SREAD pin.
READBACK FORMAT
The readback operation is initiated by writing a valid control
word to the readback register and setting the readback-enable
bit (R7_DB8 = 1). The readback can begin after the control
word has been latched with the SLE signal. SLE must be kept
high while the data is being read out. Each active edge at the
SCLK pin clocks the readback word out successively at the
SREAD pin, as shown in Figure 25, starting with the MSB first.
The data appearing at the first clock cycle following the latch
operation must be ignored.
AFC Readback
The AFC readback is valid only during the reception of FSK
signals with either the linear or correlator demodulator active.
The AFC readback value is formatted as a signed 16-bit integer
comprised of Bits RV1 to RV16, and is scaled according to the
following formula:
FREQ_RB
[Hz] = (
AFC_READBACK
×
DEMOD_CLK
)/2
15
In the absence of frequency errors, the FREQ_RB value is equal
to the IF frequency of 200 kHz. Note that, for the AFC readback
to yield a valid result, the down-converted input signal must not
fall outside the bandwidth of the analogue IF filter. At low-input
signal levels, the variation in the readback value can be
improved by averaging.
RSSI Readback
The RSSI readback operation yields valid results in Rx mode
with ASK or FSK signals. The format of the readback word is
shown in Figure 25. It is comprised of the RSSI level informa-
tion (Bits RV1 to RV7), the current filter gain (FG1, FG2), and
the current LNA gain (LG1, LG2) setting. The filter and LNA
gain are coded in accordance with the definitions in Register 9.
With the reception of ASK modulated signals, averaging of the
measured RSSI values improves accuracy. The input power can
be calculated from the RSSI readback value as outlined in the
RSSI/AGC Section.
Battery Voltage ADCIN/Temperature Sensor Readback
The battery voltage is measured at Pin VDD4. The readback
information is contained in Bits RV1 to RV7. This also applies
for the readback of the voltage at the ADCIN pin and the
temperature sensor. From the readback information, the battery
or ADCIN voltage can be determined using
V
BATTERY
= (
Battery_Voltage_Readback
)/21.1
V
ADCIN
= (
ADCIN_Voltage_Readback
)/42.1
Silicon Revision Readback
The silicon revision readback word is valid without setting any
other registers, especially directly after power-up. The silicon
revision word is coded with four quartets in BCD format. The
product code (PC) is coded with two quartets extending from
Bits RV9 to RV16. The revision code (RV) is coded with two
quartets extending from Bits RV1 to RV8. The product code
should read back as PC = #20h. The current revision code
should read as RC = #30h.
Filter Calibration Readback
The filter calibration readback word is contained in Bits RV1 to
RV8, and is for diagnostic purposes only. Using the automatic
filter calibration function, accessible through Register 6, is
recommended.
0
READBACK MODE
AFC READBACK
DB15
RV16
X
X
RV16
0
RSSI READBACK
BATTERY VOLTAGE/ADCIN/
TEMP. SENSOR READBACK
SILICON REVISION
FILTER CAL READBACK
READBACK VALUE
DB14
RV15
X
X
RV15
0
DB13
RV14
X
X
RV14
0
DB12
RV13
X
X
RV13
0
DB11
RV12
X
X
RV12
0
DB10
RV11
LG2
X
RV11
0
DB9
RV10
LG1
X
RV10
0
DB8
RV9
FG2
X
RV9
0
DB7
RV8
FG1
X
RV8
RV8
DB6
RV7
RV7
RV7
RV7
RV7
DB5
RV6
RV6
RV6
RV6
RV6
DB4
RV5
RV5
RV5
RV5
RV5
DB3
RV4
RV4
RV4
RV4
RV4
DB2
RV3
RV3
RV3
RV3
RV3
DB1
RV2
RV2
RV2
RV2
RV2
DB0
RV1
RV1
RV1
RV1
RV1
Figure 25. Readback Value Table