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參數資料
| 型號： | ADM1034ARQZ-REEL |
| 廠商： | ON Semiconductor |
| 文件頁數： | 20/38頁 |
| 文件大小： | 427K |
| 描述： | IC THERM/FAN SPEED CTRLR 16-QSOP |
| 產品變化通告： | MFG CHG Notification ADI to ON Semi |
| 標準包裝： | 2,500 |
| 功能： | 風扇控制，溫度監控器 |
| 傳感器類型： | 內部和外部 |
| 感應溫度： | -40°C ~ 125°C，外部傳感器 |
| 精確度： | ±1°C |
| 拓撲： | ADC，比較器，多路復用器，寄存器庫 |
| 輸出類型： | SMBus? |
| 輸出警報： | 是 |
| 輸出風扇： | 是 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
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ADM1034
http://onsemi.com
20
temperature channel; L or more consecutive out-of-limits on
the external 1 temperature channel; or L or more consecutive
out-of-limits on the external 2 temperature channel. The
fault queue is independent of the state of the bits in the
ALERT
status registers.
Table 23. FAULT QUEUE ADDRESS 0X06
Bits <3:0>
Fault Queue
000X
1
001X
2
01XX
3
1XXX
4
To reset the fault queue, do one of the following:
?SPAN class="pst ADM1034ARQZ-REEL_2295499_3"> SMBus ARA Command
?SPAN class="pst ADM1034ARQZ-REEL_2295499_3"> Read Status Register 1
?SPAN class="pst ADM1034ARQZ-REEL_2295499_3"> Power-On Reset
The SMBusALERT
clears, even if the condition that
caused the SMBusALERT
remains. The SMBusALERT
is
reasserted if the fault queue fills up.
Conversion Rate Register
The ADM1034 makes up to 64 measurements per second.
However, for the sake of reduced power consumption and
better noise immunity, users may run the ADM1034 at a
slower conversion rate. Better noise immunity results from
the averaging that occurs at the slower conversion rates.
Averaging does not occur at rates of 16, 32, or 64
conversions per second. Table 24 lists the available
conversion rates. Note that the current round-robin loop
must be finished for conversion rates changes to take effect.
Table 24. CONVERSION RATES
Code
Conversion Rate
0x00
0.0625
0x01
0.125
0x02
0.25
0x03
0.5
0x04
1
0x05
2
0x06
4
0x07
8
0x08
16
0x09
32
0x0A
64
0x0B to 0xFF
Reserved
THERM
I/O Timer and Limits
Pin 7 can be configured as either an input or output. As an
output it is asserted low to signal that the measured
temperature has exceeded preprogrammed temperature
limits. The output is automatically pulled high again when
the temperature falls below the THERM
Hys limit. The
value of hysteresis is programmable in Register 0x1A.
THERM
is enabled as an output by default on powerup.
Figure 32. THERM
Behavior
TEMPERATURE
LIMITS
TIME
THERM, 85?/SPAN>C
THERM
THERMHYST,
80?/SPAN>C
Once the THERM
limits are exceeded, the fans are
boosted to full speed, that is, as long as the Boost Disable Bit
(Bit 1) is not set in Configuration Register 2 (Address 0x02).
To configure THERM
as an input, the user must set the
THERM
timer bit (Bit 2) of Configuration Register 1
(Address 0x01) to 1. (It no longer operates as an output.) The
ADM1034 can then detect when the THERM
input is
asserted low. This may be connected to a trip point
temperature sensor or to the FAN_FAULT
PROCHOT
output of a CPU. With processor core voltages reducing all
the time, the threshold for the AGTL + PROCHOT
output
also reduces down as new processors become available. The
default threshold on the input is the normal CMOS
threshold. However, Pin 8 (FAN_FAULT
/REF) can also be
reconfigured as a REF input. This is done by setting Bit 7
(FAN_FAULT
/REF) in Configuration Register 4
(Address 0x04). Connect the processor V
CCP
to this input to
provide a reference for the THERM
input. The resulting
THERM
threshold is 0.75 ?V
CCP
, which is the correct
threshold for an AGTL + signal.
The ADM1034 also measures assertion times on the
THERM
input as a percentage of a time window. This time
window is programmable in Configuration Register 4
(Address 0x04) by using Bits <6:4> (THERM
% Time
Window). Values between 0.25 seconds and 8 seconds are
programmable. The assertion time as a percentage of the
time window is stored in the THERM
% On-Time Register
(Address 0x4E).
A THERM
% limit is also associated with this register. Once
the measured percentage exceeds the percentage limit, the
THERM
% Exceeded Bit (Bit 4) in Status Register 2
(Address 0x50) is asserted and an ALERT
is generated, that is,
if the mask bit is not set. If the limit is set to 0x00, an ALERT
is generated on the first assertion. If the limit is set to 0xFF, an
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