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參數資料
| 型號： | ADSP-21061L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ADSP-2106x SHARC DSP Microcomputer Family |
| 中文描述： | 的ADSP - 2106x SHARC處理器DSP的微機家庭 |
| 文件頁數： | 3/47頁 |
| 文件大小： | 367K |
| 代理商： | ADSP-21061L |
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ADSP-21061/ADSP-21061L
–3–
REV. B
Figure 1 shows a block diagram of the ADSP-21061/ADSP-
21061L, illustrating the following architectural features:
Computation Units (ALU, Multiplier and Shifter) with a
Shared Data Register File
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Interval Timer
1 Mbit On-Chip SRAM
External Port for Interfacing to Off-Chip Memory and
Peripherals
Host Port & Multiprocessor Interface
DMA Controller
Serial Ports
JTAG Test Access Port
Figure 2 shows a typical single-processor system. A multi-
processing system is shown in Figure 3.
Table I. ADSP-21061/ADSP-21061L Benchmarks (@ 50 MHz)
1024-Pt. Complex FFT
(Radix 4, with Digit Reverse)
FIR Filter (per Tap)
IIR Filter (per Biquad)
Divide (y/x)
Inverse Square Root (1/
√
x
)
DMA Transfer Rate
0.37 ms
18,221 Cycles
20 ns
80 ns
120 ns
180 ns
300 Mbytes/s
1 Cycle
4 Cycles
6 Cycles
9 Cycles
GENERAL NOTE
This data sheet represents production released specifications
for the ADSP-21061 5 V and ADSP-21061L 3.3 V proces-
sors. ADSP-21061 is used throughout this data sheet to refer to
both devices unless expressly noted.
GENERAL DESCRIPTION
The ADSP-21061 is a member of the powerful SHARC family
of floating point processors. The SHARC—Super Harvard
Architecture Computer—are signal processing microcomputers
that offer new capabilities and levels of integration and perfor-
mance. The ADSP-21061 is a 32-bit processor optimized for
high performance DSP applications. The ADSP-21061 com-
bines the ADSP-21000 DSP core with a dual-ported on-chip
SRAM and an I/O processor with a dedicated I/O bus to form a
complete system-in-a-chip.
Fabricated in a high-speed, low-power CMOS process, the
ADSP-21061 has a 20 ns instruction cycle time operating at up
to 50 MIPS. With its on-chip instruction cache, the processor can
execute every instruction in a single cycle. Table I shows perfor-
mance benchmarks for the ADSP-21061/ADSP-21061L.
The ADSP-21061 SHARC
combines a high-performance float-
ing-point DSP core with integrated, on-chip system features,
including a 1 Mbit SRAM memory, host processor interface,
DMA controller, serial ports and parallel bus connectivity for
glueless DSP multiprocessing.
S
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-21061LAS-160 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061LAS-176 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 44MHz 44MIPS 240-Pin MQFP Tray 制造商:Analog Devices 功能描述:IC MICROCOMPUTER DSP |
| ADSP-21061LASZ-176 | 功能描述:IC DSP CONTROLLER 32BIT 240MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21061LKB-160 | 功能描述:IC DSP CONTROLLER 32BIT 225BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21061LKB-176 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer Family |
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