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參數資料
| 型號： | ADSP-21061L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ADSP-2106x SHARC DSP Microcomputer Family |
| 中文描述： | 的ADSP - 2106x SHARC處理器DSP的微機家庭 |
| 文件頁數： | 32/47頁 |
| 文件大小： | 367K |
| 代理商： | ADSP-21061L |
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–32–
ADSP-21061/ADSP-21061L
REV. B
ADSP-21061 (5 V)
Min
ADSP-21061L (3.3 V)
Min
Parameter
Max
Max
Unit
Timing Requirements:
t
SDRLC
t
SDRHC
t
WDR
t
SDATDGL
t
HDATIDG
t
DATDRH
t
DMARLL
t
DMARH
Switching Characteristics:
t
DDGL
DMAG
x Low Delay after CLKIN
t
WDGH
DMAG
x High Width
t
WDGL
DMAG
x Low Width
t
HDGC
DMAG
x High Delay after CLKIN
t
DADGH
Address Select Valid to
DMAG
x High
t
DDGHA
Address Select Hold to
DMAG
x High
t
VDATDGH
Data Valid before
DMAG
x High
3
t
DATRDGH
Data Disable after
DMAG
x High
4
t
DGWRL
WR
Low before
DMAG
x Low
t
DGWRH
DMAG
x Low before
WR
High
t
DGWRR
WR
High before
DMAG
x High
t
DGRDL
RD
Low before
DMAG
x Low
t
DRDGH
RD
Low before
DMAG
x High
t
DGRDR
RD
High before
DMAG
x High
t
DGWR
DMAG
x High to
WR
,
RD
,
DMAG
x Low
DMAR
x Low Setup before CLKIN
1
DMAR
x High Setup before CLKIN
1
DMAR
x Width Low (Nonsynchronous)
Data Setup after
DMAG
x Low
2
Data Hold after
DMAG
x High
Data Valid after
DMAR
x High
2
DMAG
x Low Edge to Low Edge
DMAG
x Width High
5
5
6
5
5
6
ns
ns
ns
ns
ns
ns
ns
ns
10 + 5DT/8
10 + 5DT/8
2
2
16 + 7DT/8
16 + 7DT/8
23 + 7DT/8
6
23.5 + 7DT/8
6
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
17 + DT
–0.5
8 + 9DT/16
0
0
10 + 5DT/8 + W
1 + DT/16
0
11 + 9DT/16 + W
0
5 + 3DT/8 + HI
15 + DT/4
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
17 + DT
–1.0
8 + 9DT/16
0
0
10 + 5DT/8 + W
1 + DT/16
0
11 + 9DT/16 + W
0
5 + 3DT/8 + HI
15 + DT/4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6 – DT/8
6 – DT/8
7
2
7
2
3 + DT/16
2
3 + DT/16
2
3
3
W = (number of wait states specified in WAIT register)
×
t
CK
.
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
1
Only required for recognition in the current cycle.
2
t
is the data setup requirement if
DMAR
x is not being used to hold off completion of a write. Otherwise, if
DMAR
x low holds off completion of the write, the
data can be driven t
after
DMAR
x is brought high.
3
t
VDATDGH
is valid if
DMAR
x is not being used to hold off completion of a read. If
DMAR
x is used to prolong the read, then t
VDATDGH
= 8 + 9DT/16 + (n
×
t
CK
) where
n
4
See
System Hold Time Calculation
under Test Conditions for calculation of hold times given capacitive and dc loads.
transfer is controlled by ADDR
31-0
,
RD
,
WR
,
MS
3-0
and ACK
(not
DMAG
). For Paced Master mode, the Memory Read–Bus
Master, Memory Write–Bus Master, and Synchronous Read/
Write–Bus Master timing specifications for ADDR
31-0
,
RD
,
WR
,
MS
3-0
,
SW
, PAGE, DATA
47-0
and ACK also apply.
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes DMAR is used to initiate transfers. For hand-
shake mode, DMAG controls the latching or enabling of data
externally. For external handshake mode, the data transfer is
controlled by the ADDR
31-0
,
RD
,
WR
,
SW
, PAGE,
MS
3-0
,
ACK and
DMAG
signals. For Paced Master mode, the data
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