- 您現在的位置：買賣IC網 > PDF目錄374032 > ADSP-21061L (Analog Devices, Inc.) ADSP-2106x SHARC DSP Microcomputer Family PDF資料下載
參數資料
| 型號： | ADSP-21061L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ADSP-2106x SHARC DSP Microcomputer Family |
| 中文描述： | 的ADSP - 2106x SHARC處理器DSP的微機家庭 |
| 文件頁數： | 5/47頁 |
| 文件大小： | 367K |
| 代理商： | ADSP-21061L |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
ADSP-21061/ADSP-21061L
–5–
REV. B
Off-Chip Memory and Peripherals Interface
The ADSP-21061’s external port provides the processor’s inter-
face to off-chip memory and peripherals. The 4-gigaword off-
chip address space is included in the ADSP-21061’s unified
address space. The separate on-chip buses—for program
memory, data memory and I/O—are multiplexed at the external
port to create an external system bus with a single 32-bit address
bus and a single 48-bit (or 32-bit) data bus. The on-chip
Super Harvard Architecture provides three-bus performance,
while the off-chip unified address space gives flexibility to the
designer.
Addressing of external memory devices is facilitated by on-chip
decoding of high order address lines to generate memory bank
select signals. Separate control lines are also generated for sim-
plified addressing of page-mode DRAM. The ADSP-21061
provides programmable memory wait states and external memory
acknowledge controls to allow interfacing to DRAM and peripher-
als with variable access, hold and disable time requirements.
Host Processor Interface
The ADSP-21061’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with
little additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-21061’s exter-
nal port and is memory-mapped into the unified address space.
Two channels of DMA are available for the host interface; code
and data transfers are accomplished with low software overhead.
The host processor requests the ADSP-21061’s external bus
with the host bus request (
HBR
), host bus grant (
HBG
) and
ready (REDY) signals. The host can directly read and write the
internal memory of the ADSP-21061, and can access the
DMA channel setup and mailbox registers. Vector interrupt
support is provided for efficient execution of host commands.
DMA Controller
The ADSP-21061’s on-chip DMA controller allows zero-
overhead, nonintrusive data transfers without processor inter-
vention. The DMA controller operates independently and
invisibly to the processor core, allowing DMA operations to
occur while the core is simultaneously executing its program
instructions.
DMA transfers can occur between the ADSP-21061’s internal
memory and either external memory, external peripherals, or a
host processor. DMA transfers can also occur between the
ADSP-21061’s internal memory and its serial ports. DMA
transfers between external memory and external peripheral
devices are another option. External bus packing to 16-, 32-
or 48-bit words is performed during DMA transfers.
Six channels of DMA are available on the ADSP-21061—four
via the serial ports, and two via the processor’s external port (for
either host processor, other ADSP-21061s, memory or I/O
transfers). Programs can be downloaded to the ADSP-21061
using DMA transfers. Asynchronous off-chip peripherals can
control two DMA channels using DMA Request/Grant lines
(
DMAR
1-2
,
DMAG
1-2
). Other DMA features include interrupt
generation upon completion of DMA transfers and DMA chain-
ing for automatic linked DMA transfers.
Serial Ports
The ADSP-21061 features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
the full clock rate of the processor, providing each with a maxi-
mum data rate of 40 Mbit/s. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports offers TDM
multichannel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from three
bits to 32 bits. They offer selectable synchronization and trans-
mit modes as well as optional
μ
-law or A-law companding.
Serial port clocks and frame syncs can be internally or externally
generated. The serial ports also include keyword and keymask
features to enhance interprocessor communication.
Multiprocessing
The ADSP-21061 offers powerful features tailored to multipro-
cessing DSP systems. The unified address space allows direct
interprocessor accesses of each ADSP-21061’s internal memory.
Distributed bus arbitration logic is included on-chip for simple,
glueless connection of systems containing up to six ADSP-21061s
and a host processor. Master processor changeover incurs only
one cycle of overhead. Bus arbitration is selectable as either
fixed or rotating priority. Bus lock allows indivisible read-modify-
write sequences for semaphores. A vector interrupt is provided
for interprocessor commands. Maximum throughput for inter-
processor data transfer is 500 Mbytes/sec over the external port.
Broadcast writes allow simultaneous transmission of data to
all ADSP-21061s and can be used to implement reflective
semaphores.
Program Booting
The internal memory of the ADSP-21061 can be booted at
system power-up from either an 8-bit EPROM or a host proces-
sor. Selection of the boot source is controlled by the
BMS
(Boot
Memory Select), EBOOT (EPROM Boot), and LBOOT (Host
Boot) pins. 32-bit and 16-bit host processors can be used for
booting. See the
BMS
pin in the Pin Function Descriptions
section of this data sheet.
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-21061LAS-160 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061LAS-176 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061KS-160 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061KS-200 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061LKB-160 | ADSP-2106x SHARC DSP Microcomputer Family |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-21061LAS-160 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061LAS-176 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 44MHz 44MIPS 240-Pin MQFP Tray 制造商:Analog Devices 功能描述:IC MICROCOMPUTER DSP |
| ADSP-21061LASZ-176 | 功能描述:IC DSP CONTROLLER 32BIT 240MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21061LKB-160 | 功能描述:IC DSP CONTROLLER 32BIT 225BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21061LKB-176 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer Family |
發布緊急采購，3分鐘左右您將得到回復。