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參數資料
| 型號： | ADSP-21160NCB-TBD |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無電容，NMOS管，150mA的低壓差穩壓器的反向電流保護 |
| 文件頁數： | 13/53頁 |
| 文件大小： | 1680K |
| 代理商： | ADSP-21160NCB-TBD |
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
13
REV. PrB
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
April 2002
ADSP-21160N SPECIFICATIONS
PRELIMINARY TECHNICAL DATA
RECOMMENDED OPERATING CONDITIONS
Signal
Parameter
1
C Grade
K Grade
Unit
Min
Max
Min
Max
V
DDINT
AV
DD
V
DDEXT
T
CASE
V
IH1
V
IH2
V
IL
Internal (Core) Supply Voltage
Analog (PLL) Supply Voltage
External (I/O) Supply Voltage
Case Operating Temperature
2
High Level Input Voltage
3
, @ V
DDEXT
=Max
High Level Input Voltage
4
, @ V
DDEXT
=Max
Low Level Input Voltage
3,4
, @ V
DDEXT
=Min
1.8
1.8
3.13
–40
2.2
2.3
–0.5
2.0
2.0
3.47
+100
V
DDEXT
+0.5
V
DDEXT
+0.5
0.8
1.8
1.8
3.13
0
2.2
2.3
–0.5
2.0
2.0
3.47
85
V
DDEXT
+0.5
V
DDEXT
+0.5
0.8
V
V
V
oC
V
V
V
1
Specifications subject to change without notice.
2
See
Environmental Conditions on page 48
for information on thermal specifications.
3
Applies to input and bidirectional pins: DATA63–0, ADDR31–0,
RDx
,
WRx
, ACK,
SBTS
,
IRQ2–0
, FLAG3–0,
HBG
,
CS
,
DMAR1
,
DMAR2
,
BR6–1
,
ID2–0, RPBA,
PA
, BRST, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT,
BMS
, TMS, TDI, TCK,
HBR
, DR0, DR1,
TCLK0, TCLK1, RCLK0, RCLK1.
4
Applies to input pins: CLKIN,
RESET
,
TRST
.
ELECTRICAL CHARACTERISTICS
Parameter
1
Test Conditions
@ V
DDEXT
=Min, I
OH
=–2.0 mA
3
@ V
DDEXT
=Min, I
OL
=4.0 mA
3
@ V
DDEXT
=Max, V
IN
=V
DD
Max
@ V
DDEXT
=Max, V
IN
=0 V
@ V
DDEXT
=Max, V
IN
=0 V
@ V
DDEXT
=Max, V
IN
=0 V
@ V
DDEXT
=Max, V
IN
=V
DD
Max
@ V
DDEXT
=Max, V
IN
=0 V
@ V
DDEXT
=Max, V
IN
=V
DD
Max
C and K Grades
Unit
Min
Max
V
OH
V
OL
I
IH
I
IL
I
ILPU1
I
ILPU2
I
OZH
I
OZL
I
OZHPD
High Level Output Voltage
2
Low Level Output Voltage
2
High Level Input Current
4,5,6
Low Level Input Current
4
Low Level Input Current Pull-Up1
5
Low Level Input Current Pull-Up2
6
Three-State Leakage Current
7,8,9,10
Three-State Leakage Current
7
Three-State Leakage Current
Pull-Down
10
Three-State Leakage Current
Pull-Up1
8
Three-State Leakage Current
Pull-Up2
9
Three-State Leakage Current
11
Three-State Leakage Current
11
Supply Current (Internal)
12
Supply Current (Internal)
13
Supply Current (Internal)
14
Supply Current (Idle)
15
Supply Current (Analog)
16
Input Capacitance
17,18
2.4
V
V
μA
μA
μA
μA
μA
μA
μA
0.4
10
10
250
500
10
10
250
I
OZLPU1
@ V
DDEXT
=Max, V
IN
=0 V
250
μA
I
OZLPU2
@ V
DDEXT
=Max, V
IN
=0 V
500
μA
I
OZHA
I
OZLA
I
DD-INPEAK
I
DD-INHIGH
I
DD-INLOW
I
DD-IDLE
AI
DD
C
IN
@ V
DDEXT
=Max, V
IN
=V
DD
Max
@ V
DDEXT
=Max, V
IN
=0 V
t
CCLK
=10.5 ns, V
DDINT
=Max
t
CCLK
=10.5 ns, V
DDINT
=Max
t
CCLK
=10.5 ns, V
DDINT
=Max
t
CCLK
=10.5 ns, V
DDINT
=Max
@AV
DD
=Max
f
IN
=1 MHz, T
CASE
=25°C,
V
IN
=2.5 V
25
4
1400
875
625
400
10
4.7
μA
mA
mA
mA
mA
mA
mA
pF
1
Specifications subject to change without notice.
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