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參數(shù)資料
| 型號(hào)： | ADSP-21160NCB-TBD |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無(wú)電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù) |
| 文件頁(yè)數(shù)： | 41/53頁(yè) |
| 文件大小： | 1680K |
| 代理商： | ADSP-21160NCB-TBD |
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PRELIMINARY TECHNICAL DATA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
41
REV. PrB
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
April 2002
Serial Ports
To determine whether communication is possible between two devices at clock speed n, the following specifications must
be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
Table 21. Serial Ports—External Clock
Parameter
Timing Requirements:
t
SFSE
t
HFSE
t
SDRE
t
HDRE
t
SCLKW
t
SCLK
Min
Max
Unit
TFS/RFS Setup Before TCLK/RCLK
1
TFS/RFS Hold After TCLK/RCLK
1,2
Receive Data Setup Before RCLK
1
Receive Data Hold After RCLK
1
TCLK/RCLK Width
TCLK/RCLK Period
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
3.5
4
1.5
4
8
2t
CCLK
ns
ns
ns
ns
ns
ns
Table 22. Serial Ports—Internal Clock
Parameter
Timing Requirements:
t
SFSI
t
HFSI
t
SDRI
t
HDRI
Min
Max
Unit
TFS Setup Before TCLK
1
; RFS Setup Before RCLK
1
TFS/RFS Hold After TCLK/RCLK
1,2
Receive Data Setup Before RCLK
1
Receive Data Hold After RCLK
1
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
8
t
CCLK
/2 + 1
6.5
3
ns
ns
ns
ns
Table 23. Serial Ports—External or Internal Clock
Parameter
Switching Characteristics:
t
DFSE
t
HOFSE
Min
Max
Unit
RFS Delay After RCLK (Internally Generated RFS)
1
RFS Hold After RCLK (Internally Generated RFS)
1
1
Referenced to drive edge.
13
ns
ns
3
Table 24. Serial Ports—External Clock
Parameter
Switching Characteristics:
t
DFSE
t
HOFSE
t
DDTE
t
HDTE
Min
Max
Unit
TFS Delay After TCLK (Internally Generated TFS)
1
TFS Hold After TCLK (Internally Generated TFS)
1
Transmit Data Delay After TCLK
1
Transmit Data Hold After TCLK
1
1
Referenced to drive edge.
13
ns
ns
ns
ns
3
16
0
Table 25. Serial Ports—Internal Clock
Parameter
Switching Characteristics:
t
DFSI
t
HOFSI
Min
Max
Unit
TFS Delay After TCLK (Internally Generated TFS)
1
TFS Hold After TCLK (Internally Generated TFS)
1
4.5
ns
ns
–1.5
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