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參數資料
| 型號： | ADSP-21160NCB-TBD |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無電容，NMOS管，150mA的低壓差穩壓器的反向電流保護 |
| 文件頁數： | 8/53頁 |
| 文件大?。?/td> | 1680K |
| 代理商： | ADSP-21160NCB-TBD |
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
8
REV. PrB
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
April 2002
PRELIMINARY TECHNICAL DATA
Also, the clearance (length, width, and height) around the
header must be considered. Leave a clearance of at least
0.15" and 0.10" around the length and width of the header,
and reserve a height clearance to attach and detach the pod
connector.
As can be seen in
Figure 6
, there are two sets of signals on
the header. There are the standard JTAG signals TMS,
TCK, TDI, TDO,
TRST
, and
EMU
used for emulation
purposes (via an emulator). There are also secondary JTAG
signals BTMS, BTCK, BTDI, and
BTRST
that are option-
ally used for board-level (boundary scan) testing.
When the emulator is not connected to this header, place
jumpers across BTMS, BTCK,
BTRST
, and BTDI as
shown in
Figure 7
. This holds the JTAG signals in the
correct state to allow the DSP to run free. Remove all the
jumpers when connecting the emulator to the JTAG header.
JTAG Emulator Pod Connector
Figure 8
details the dimensions of the JTAG pod connector
at the 14-pin target end.
Figure 9
displays the keep-out area
for a target board header. The keep-out area allows the pod
connector to properly seat onto the target board header.
This board area should contain no components (chips,
resistors, capacitors, etc.). The dimensions are referenced
to the center of the 0.25" square post pin.
Design-for-Emulation Circuit Information
For details on target board design issues including: single
processor connections, multiprocessor scan chains, signal
buffering, signal termination, and emulator pod logic, see
the
EE-68: Analog Devices JTAG Emulation Technical
Reference
on the Analog Devices website—use site search on
“EE-68” (www.analog.com). This document is updated
regularly to keep pace with improvements to emulator
support.
Additional Information
This data sheet provides a general overview of the
ADSP-21160N architecture and functionality. For detailed
information on the ADSP-2116x Family core architecture
and instruction set, refer to the ADSP-2116x
SHARC DSP
Hardware Reference
.
Figure 6. JTAG Target Board Connector for JTAG
Equipped Analog Devices DSP (Jumpers in
Place)
TOP VIEW
13
14
11
12
9
10
9
7
8
5
6
3
4
1
2
EMU
GND
TMS
TCK
TRST
TDI
TDO
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
Figure 7. JTAG Target Board Connector with No Local
Boundary Scan
Figure 8. JTAG Pod Connector Dimensions
Figure 9. JTAG Pod Connector Keep-Out Area
TOP VIEW
13
14
11
12
9
10
9
7
8
5
6
3
4
1
2
EMU
GND
TMS
TCK
TRST
TDI
TDO
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
0.64"
0.88"
0.24"
0.10"
0.15"
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