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參數資料
| 型號： | ADSP-21160NKB-95 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 64-BIT, 47.5 MHz, OTHER DSP, PBGA400 |
| 封裝： | 27 X 27 MM, METRIC, PLASTIC, BGA-400 |
| 文件頁數： | 10/53頁 |
| 文件大小： | 1680K |
| 代理商： | ADSP-21160NKB-95 |
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
10
REV. PrB
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
April 2002
PRELIMINARY TECHNICAL DATA
WRH
I/O/T
Memory Write High Strobe.
WRH
is asserted when ADSP-21160N writes to the high
word of external memory or internal memory of other ADSP-21160Ns. External devices
must assert
WRH
for writing to ADSP-21160N’s high word of internal memory. In a
multiprocessing system,
WRH
is driven by the bus master. WRH has a 20k
internal
pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.
DRAM Page Boundary. The ADSP-21160N asserts this pin to signal that an external
DRAM page boundary has been crossed. DRAM page size must be defined in the
ADSP-21160N’s memory control register (WAIT). DRAM can only be implemented
in external memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses.
In a multiprocessing system PAGE is output by the bus master. A keeper latch on the
DSP’s PAGE pin maintains the output at the level it was last driven (only enabled on
the ADSP-21160N with ID2–0 = 00x).
Sequential Burst Access. BRST is asserted by ADSP-21160N or a host to indicate that
data associated with consecutive addresses is being read or written. A slave device
samples the initial address and increments an internal address counter after each
transfer. The incremented address is not pipelined on the bus. If the burst access is a
read from host to ADSP-21160N, ADSP-21160N automatically increments the address
as long as BRST is asserted. BRST is asserted after the initial access of a burst transfer.
It is asserted for every cycle after that, except for the last data request cycle (denoted by
RDx
or
WRx
asserted and BRST negated). A keeper latch on the DSP’s BRST pin
maintains the input at the level it was last driven (only enabled on the ADSP-21160N
with ID2–0 = 00x).
Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to
an external memory access. ACK is used by I/O devices, memory controllers, or other
peripherals to hold off completion of an external memory access. The ADSP-21160N
deasserts ACK as an output to add wait states to a synchronous access of its internal
memory. ACK has a 2k
internal pull-up resistor that is enabled on the ADSP-21160N
with ID2–0 = 00x.
Suspend Bus and Three-State. External devices can assert
SBTS
(low) to place the
external bus address, data, selects, and strobes in a high impedance state for the following
cycle. If the ADSP-21160N attempts to access external memory while
SBTS
is asserted,
the processor will halt and the memory access will not be completed until
SBTS
is
deasserted.
SBTS
should only be used to recover from host processor and/or
ADSP-21160N deadlock or used with a DRAM controller.
Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be
either edge-triggered or level-sensitive.
Flag Pins. Each is configured via control bits as either an input or output. As an input,
it can be tested as a condition. As an output, it can be used to signal external peripherals.
Timer Expired. Asserted for four Core Clock cycles when the timer is enabled and
TCOUNT decrements to zero.
Host Bus Request. Must be asserted by a host processor to request control of the
ADSP-21160N’s external bus. When
HBR
is asserted in a multiprocessing system, the
ADSP-21160N that is bus master will relinquish the bus and assert
HBG
. To relinquish
the bus, the ADSP-21160N places the address, data, select, and strobe lines in a high
impedance state.
HBR
has priority over all ADSP-21160N bus requests (
BR6–1
) in a
multiprocessing system.
Host Bus Grant. Acknowledges an
HBR
bus request, indicating that the host processor
may take control of the external bus.
HBG
is asserted (held low) by the ADSP-21160N
until
HBR
is released. In a multiprocessing system,
HBG
is output by the
ADSP-21160N bus master and is monitored by all others. After
HBR
is asserted, and
before
HBG
is given,
HBG
will float for 1 tCLK (1 CLKIN cycle). To avoid erroneous
grants,
HBG
should be pulled up with a 20k to 50k ohm external resistor.
Chip Select. Asserted by host processor to select the ADSP-21160N.
PAGE
O/T
BRST
I/O/T
ACK
I/O/S
SBTS
I/S
IRQ2–0
I/A
FLAG3–0
I/O/A
TIMEXP
O
HBR
I/A
HBG
I/O
CS
I/A
Table 2. Pin Function Descriptions (Continued)
Pin
Type
Function
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-21160N | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| ADSP-21160NCB-TBD | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| ADSP-21161N | DSP Microcomputer |
| ADSP-21161NCCA-100 | DSP Microcomputer |
| ADSP-21161NKCA-100 | DSP Microcomputer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-21160NKB-X | 制造商:Analog Devices 功能描述: |
| ADSP-21160NKBZ-100 | 功能描述:IC DSP CONTROLLER 32BIT 400-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161N | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21161NCCA-100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NCCAZ100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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