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參數(shù)資料
| 型號： | ADSP-21160NKB-95 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 64-BIT, 47.5 MHz, OTHER DSP, PBGA400 |
| 封裝： | 27 X 27 MM, METRIC, PLASTIC, BGA-400 |
| 文件頁數(shù)： | 17/53頁 |
| 文件大小： | 1680K |
| 代理商： | ADSP-21160NKB-95 |
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
17
REV. PrB
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
April 2002
PRELIMINARY TECHNICAL DATA
Power-up Sequencing
During the power up sequence of the DSP, differences in
the ramp up rates and activation time between the two power
supplies can cause current to flow in the I/O ESD protection
circuitry. To prevent this damage to the ESD diode protec-
tion circuitry, Analog Devices, Inc. recommends including
a bootstrap Schottky diode (see
Figure 11 on page 18
. The
bootstrap Schottky diode connected between the 1.9V and
3.3V power supplies protects the ADSP-21160N from
partially powering the 3.3V supply. Including a Schottky
diode will shorten the delay between the supply ramps and
thus prevent damage to the ESD diode protection circuitry.
With this technique, if the 1.9V rail rises ahead of the 3.3V
rail, the Schottky diode pulls the 3.3V rail along with the
1.9V rail.
Table 4. Power-up Sequencing
Parameter
Timing Requirements:
t
RSTVDD
t
IVDDEVDD
t
CLKVDD
t
CLKRST
t
PLLRST
Switching Characteristics:
t
CORERST
Min
Max
Unit
RESET
low before V
DDINT
/V
DDEXT
on
V
DDINT
on before V
DDEXT
CLKIN running after valid V
DDINT
/V
DDEXT
1
CLKIN valid before
RESET
de-asserted
PLL control setup before
RESET
de-asserted
0
-50
0
10
3
TBD
4
ns
ms
ms
μs
ms
200
200
2
DSP core reset de-asserted after RESET de-asserted
4096*t
CK
4,5
ms
1
Valid V
DDINT
/V
DDEXT
assumes that the supplies are fully ramped to their 1.9 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds
of milliseconds, depending on the design of the power supply subsystem.
2
CLKIN should be driven coincident with power-up to avoid an undefined state in internal gates, which may cause excess current flow.
3
Assumes a stable CLKIN signal after meeting worst case start up timing of oscillators. Refer to your oscillator manufacturer’s data sheet for start up time.
4
Based on CLKIN cycles.
5
CORERST
is an internal signal only. The 4096 cycle count is dependent on t
SRST
specification. If setup time is not met, one additional CLKIN cycle may
be added to the core reset time, resulting in 4097 cycles maximum.
Figure 10. Power-up Sequencing
CLKIN
RESET
t
RSTVDD
VDDEXT
VDDINT
t
IVDDEVDD
t
CLKVDD
t
CLKRST
t
PLLRST
t
CORERST
CLK_CFG3-0
CORERST
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| ADSP-21161N | DSP Microcomputer |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21160NKB-X | 制造商:Analog Devices 功能描述: |
| ADSP-21160NKBZ-100 | 功能描述:IC DSP CONTROLLER 32BIT 400-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161N | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21161NCCA-100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NCCAZ100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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