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參數(shù)資料
| 型號： | ADSP-21364 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | SHARC處理器 |
| 文件頁數(shù)： | 17/52頁 |
| 文件大小： | 853K |
| 代理商： | ADSP-21364 |
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ADSP-21364
Preliminary Technical Data
Rev. PrB
|
Page 17 of 52
|
September 2004
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control (
Table 8
).
Figure 5
shows Core to CLKIN ratios of 6:1, 16:1 and 32:1 with
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the
ADSP-2136x SHARC Processor Programming Reference
.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 38 on page 43
under Test Conditions for voltage refer-
ence levels.
Switching Characteristics
specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements
apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Table 8. ADSP-21364 CLKOUT and CCLK Clock
Generation Operation
Timing
Requirements
CLKIN
CCLK
Description
Calculation
Input Clock
Core Clock
1/t
CK
1/t
CCLK
Table 9. Clock Periods
Timing
Requirements
t
CK
t
CCLK
t
PCLK
t
SCLK
t
SPICLK
Description
1
1
where:
SR = serial port-to-core clock ratio (wide range, determined by
SPORT CLKDIV)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by
SPIBAUD register)
DAI_Px = Serial Port Clock
SPICLK = SPI Clock
CLKIN Clock Period
(Processor) Core Clock Period
(Peripheral) Clock Period = 2 × t
CCLK
Serial Port Clock Period = (t
PCLK
) × SR
SPI Clock Period = (t
PCLK
) × SPIR
Figure 5. Core Clock and System Clock Relationship to CLKIN
CLKIN
CCLK
(CORECLOCK)
PLLILCLK
XTAL
XTAL
OSC
PLL
6:1, 16:1,
32:1
CLKOUT
CLK-CFG[1:0]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21364BBC-1AA | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADSP-21364BBC-1AAZ | 制造商:Analog Devices 功能描述:DSP 32BIT SHARC 333MHZ 136CSPBGA |
| ADSP-21364BBCZ-1AA | 功能描述:IC DSP 32BIT 333MHZ 136-CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21364BSQZ-1AX | 制造商:Analog Devices 功能描述:333 MHZ, PROCESSOR W/ON CHIP ROM,S/PDIF - Trays |
| ADSP-21364BSWZ-1AA | 功能描述:IC DSP 32BIT 333MHZ EPAD 144LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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