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參數資料
| 型號： | ADUC836BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, Dual 16-Bit-ADCs with Embedded 62 kB Flash MCU |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 14 X 14 MM, MO-022-AC-1, MQFP-52 |
| 文件頁數： | 14/80頁 |
| 文件大?。?/td> | 5913K |
| 代理商： | ADUC836BS |
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ADuC836
–14–
When accessing the internal XRAM, the P0 and P2 port pins, as
well as the
RD
and
WR
strobes, will not be output as per a stan-
dard 8051 MOVX instruction. This allows the user to use these
port pins as standard I/O.
The upper 1792 bytes of the internal XRAM can be configured
to be used as an extended 11-bit stack pointer. By default, the
stack will operate exactly like an 8052 in that it will roll over from
FFH to 00H in the general-purpose RAM. On the ADuC836
however, it is possible (by setting CFG836.7) to enable the 11-bit
extended stack pointer. In this case, the stack will roll over from
FFH in RAM to 0100H in XRAM. The 11-bit stack pointer is
visible in the SP and SPH SFRs. The SP SFR is located at 81H
as with a standard 8052. The SPH SFR is located at B7H. The
3 LSBs of this SFR contain the three extra bits necessary to
extend the 8-bit stack pointer into an 11-bit stack pointer.
UPPER 1792
BYTES OF
ON-CHIP XRAM
(DATA + STACK
FOR EXSP = 1,
DATA ONLY
FOR EXSP = 0)
256 BYTES OF
ON-CHIP DATA
RAM
(DATA +
STACK)
LOWER 256
BYTES OF
ON-CHIP XRAM
(DATA ONLY)
00H
FFH
00H
07FFH
CFG836.7 = 0
CFG836.7 = 1
100H
Figure 4. Extended Stack Pointer Operation
External Data Memory (External XRAM)
Just like a standard 8051 compatible core, the ADuC836 can
access external data memory using a MOVX instruction. The
MOVX instruction automatically outputs the various control
strobes required to access the data memory.
The ADuC836, however, can access up to 16 Mbytes of external
data memory. This is an enhancement of the 64 Kbytes external
data memory space available on a standard 8051 compatible core.
The external data memory is discussed in more detail in the
ADuC836 Hardware Design Considerations section.
SPECIAL FUNCTION REGISTERS (SFRS)
The SFR space is mapped into the upper 128 bytes of internal
data memory space and accessed by direct addressing only. It
provides an interface between the CPU and all on-chip periph-
erals. A block diagram showing the programming model of the
ADuC836 via the SFR area is shown in Figure 5.
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
62 KBYTE ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE FLASH/EE
PROGRAM MEMORY
8051
COMPATIBLE
CORE
OTHER ON-CHIP
PERIPHERALS
TEMP SENSOR
CURRENT SOURCES
12-BIT DAC
SERIAL I/O
WDT, PSM
TIC, PLL
DUAL
-
ADCs
4 KBYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE DATA
MEMORY
256 BYTES RAM
2K XRAM
Figure 5. Programming Model
All registers, except the Program Counter (PC) and the four
general-purpose register banks, reside in the SFR area. The SFR
registers include control, configuration, and data registers that
provide an interface between the CPU and all on-chip peripherals.
Accumulator SFR (ACC)
ACC is the Accumulator Register, which is used for math
operations including addition, subtraction, integer multiplication,
and division, and Boolean bit manipulations. The mnemonics for
accumulator-specific instructions, refer to the Accumulator as A.
B SFR (B)
The B Register is used with the ACC for multiplication and
division operations. For other instructions, it can be treated as a
general-purpose scratch pad register.
Data Pointer (DPTR)
The Data Pointer is made up of three 8-bit registers, named DPP
(page byte), DPH (high byte), and DPL (low byte). These are
used to provide memory addresses for internal and external code
access and external data access. It may be manipulated as a 16-bit
register (DPTR = DPH, DPL), although INC DPTR instructions
will automatically carry over to DPP, or as three independent 8-bit
registers (DPP, DPH, DPL).
The ADuC836 supports dual data pointers. For more information,
refer to the Dual Data Pointer section.
REV. A
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| ADUC836BS | 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
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