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參數(shù)資料
| 型號(hào)： | ADUC836BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, Dual 16-Bit-ADCs with Embedded 62 kB Flash MCU |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 14 X 14 MM, MO-022-AC-1, MQFP-52 |
| 文件頁數(shù)： | 46/80頁 |
| 文件大小： | 5913K |
| 代理商： | ADUC836BS |
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ADuC836
–46–
I
2
C SERIAL INTERFACE
The ADuC836 supports a fully licensed
*
I
2
C serial interface. The
I
2
C interface is implemented as a full hardware slave and soft-
ware master. SDATA (Pin 27) is the data I/O pin and SCLOCK
(Pin 26) is the serial clock. These two pins are shared with the
MOSI and SCLOCK pins of the on-chip SPI interface. Therefore
the user can enable only one interface or the other at any given
time (see SPE in Table XXI). Application Note uC001 describes
the operation of this interface as implemented and is available from
www.analog.com/microconverter.
Three SFRs are used to control the I
2
C interface. These are
described below.
Table XXII. I2CCON SFR Bit Designations
Bit Name Description
7 MDO I
2
C Software Master Data Output Bit (Master Mode Only).
This data bit is used to implement a master I
2
C transmitter interface in software. Data written to this bit will
be output on the SDATA pin if the data output enable (MDE) bit is set.
6 MDE I
2
C Software Master Data Output Enable Bit (Master Mode Only).
Set by user to enable the SDATA pin as an output (Tx).
Cleared by user to enable SDATA pin as an input (Rx).
5 MCO I
2
C Software Master Clock Output Bit (Master Mode Only).
This data bit is used to implement a master I
2
C transmitter interface in software. Data written to this bit will
be output on the SCLOCK pin.
4 MDI I
2
C Software Master Data Input Bit (Master Mode Only).
This data bit is used to implement a master I
2
C receiver interface in software. Data on the SDATA pin is
latched into this bit on SCLOCK if the data output enable (MDE) bit is 0.
3 I2CM I
2
C Master/Slave Mode Bit.
Set by user to enable I
2
C software Master mode.
Cleared by user to enable I
2
C hardware Slave mode.
2 I2CRS I
2
C Reset Bit (Slave Mode Only).
Set by user to reset the I
2
C interface.
Cleared by user code for normal I
2
C operation.
1 I2CTX I
2
C Direction Transfer Bit (Slave Mode Only).
Set by MicroConverter if the interface is transmitting.
Cleared by the MicroConverter if the interface is receiving.
0 I2CI I
2
C Interrupt Bit (Slave Mode Only).
Set by the MicroConverter after a byte has been transmitted or received.
Cleared automatically when the user code reads the I2CDAT SFR (see I2CDAT below).
I2CCON I
2
C Control Register
SFR Address E8H
Power-On Default Value 00H
Bit Addressable Yes
I2CADD I
2
C Address Register
Function Holds the I
2
C peripheral address for the part. It may be overwritten by the user code. Application Note uC001
at
www.analog.com/microconverter
describes the format of the I
2
C standard 7-bit address in detail.
SFR Address 9BH
Power-On Default Value 55H
Bit Addressable No
I2CDAT I
2
C Data Register
Function The I2CDAT SFR is written by the user to transmit data over the I
2
C interface or read by user code to read
data just received by the I
2
C interface. Accessing I2CDAT automatically clears any pending I
2
C interrupt
and the I2CI bit in the I2CCON SFR. User software should access I2CDAT only once per interrupt cycle.
SFR Address 9AH
Power-On Default Value 00H
Bit Addressable No
*
Purchase of licensed I
2
C components of Analog Devices or one of its sublicensed associated companies conveys a license for the purchaser under the Philips I
2
C
Patent Rights to use these components in an I
2
C system provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
REV. A
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| ADUC836BS | 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
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