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參數資料
| 型號： | CY7C1298F-133AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 1-Mbit (64K x 18) Pipelined DCD Sync SRAM |
| 中文描述： | 64K X 18 STANDARD SRAM, 4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數： | 1/15頁 |
| 文件大小： | 332K |
| 代理商： | CY7C1298F-133AC |
1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298F
Cypress Semiconductor Corporation
Document #: 38-05417 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised April 7, 2004
Features
Registered inputs and outputs for pipelined operation
Optimal for performance (Double-Cycle deselect)
— Depth expansion without wait state
64K × 18-bit common I/O architecture
3.3V –5% and +10% core power supply (V
DD
)
3.3V I/O supply (V
DDQ
)
Fast clock-to-output times
— 3.5ns (for 166-MHz device)
— 4.0ns (for 133-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous Output Enable
JEDEC-standard 100-pin TQFP package and pinout
“ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1298F SRAM integrates 65,536x18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
), depth-expansion Chip Enables (CE
2
and
CE
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
controlled by the byte write control inputs. GW active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
The CY7C1298F operates from a +3.3V core power supply
while all outputs operate with a +3.3V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
166 MHz
3.5
240
40
133 MHz
4.0
225
40
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded areas contain advance information. Please contact your local CYpress sales representative for availability of these parts.
Note:
1. . For best–practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
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