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參數(shù)資料
型號(hào): EFM32-TG110F32-SK
廠商: Energy Micro
文件頁數(shù): 9/136頁
文件大小: 0K
描述: IC MICRO KIT GECKO 24QFN
標(biāo)準(zhǔn)包裝: 1
系列: Tiny Gecko
套件類型: 微控制器
值: 2 件 - 閃存 - 32KB
包裝: 紙板盒
安裝類型: 表面貼裝
包括封裝: 24-QFN
工具箱內(nèi)容: (2) 914-1033-2-ND - MCU 32BIT 32KB FLASH 24-QFN
其它名稱: 914-1022
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
106
www.energymicro.com
MMARVALID
MSTKERR
MUNSTKERR
DACCVIOL
IACCVIOL
Reserved
7 6 5 4 3 2 1 0
Table 4.26. MMFSR bit assignments
Bits
Name
Function
[7]
MMARVALID
Memory Management Fault Address Register (MMAR) valid flag:
0 = value in MMAR is not a valid fault address
1 = MMAR holds a valid fault address.
If a memory management fault occurs and is escalated to a hard fault because of priority, the
hard fault handler must set this bit to 0. This prevents problems on return to a stacked active
memory management fault handler whose MMAR value has been overwritten.
[6:5]
-
Reserved.
[4]
MSTKERR
Memory manager fault on stacking for exception entry:
0 = no stacking fault
1 = stacking for an exception entry has caused one or more access violations.
When this bit is 1, the SP is still adjusted but the values in the context area on the stack might
be incorrect. The processor has not written a fault address to the MMAR.
[3]
MUNSTKERR
Memory manager fault on unstacking for a return from exception:
0 = no unstacking fault
1 = unstack for an exception return has caused one or more access violations.
This fault is chained to the handler. This means that when this bit is 1, the original return stack
is still present. The processor has not adjusted the SP from the failing return, and has not
performed a new save. The processor has not written a fault address to the MMAR.
[2]
-
Reserved
[1]
DACCVIOL
Data access violation flag:
0 = no data access violation fault
1 = the processor attempted a load or store at a location that does not permit the operation.
When this bit is 1, the PC value stacked for the exception return points to the faulting
instruction. The processor has loaded the MMAR with the address of the attempted access.
[0]
IACCVIOL
Instruction access violation flag:
0 = no instruction access violation fault
1 = the processor attempted an instruction fetch from a location that does not permit execution.
This fault occurs on any access to an XN region, even when the MPU is disabled or not present
in the device.
When this bit is 1, the PC value stacked for the exception return points to the faulting
instruction. The processor has not written a fault address to the MMAR.
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