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bit of SRD controls the first subregion, and the most significant bit controls the last subregion. Disabling
a subregion means another region overlapping the disabled range matches instead. If no other enabled
region overlaps the disabled subregion the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions, With regions of these sizes, you must set
the SRD field to 0x00, otherwise the MPU behavior is Unpredictable.
4.5.8.3.1 Example of SRD use
Two regions with the same base address overlap. Region one is 128KB, and region two is 512KB. To
ensure the attributes from region one apply to the first128KB region, set the SRD field for region two to
b00000011 to disable the first two subregions, as the figure shows.
Region 1
Disabled subregion
Region 2, wit h
subregions
Base address of bot h regions
Offset from
base address
0
64KB
128KB
192KB
256KB
320KB
384KB
448KB
512KB
4.5.9 MPU design hints and tips
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the
interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
except for the RASR, it must use aligned word accesses
for the RASR it can use byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to
prevent any previous region settings from affecting the new MPU setup.
4.5.9.1 MPU configuration for a microcontroller
The EFM32 devices has only a single processor and information on Shareability and cache behavior is
not used. In such a system, program the MPU as follows:
Table 4.48. Memory region attributes for a microcontroller
Memory region
TEX
C
B
S
Memory type and attributes
Flash memory
b000
1
0
Normal memory, Non-shareable, write-through
Internal SRAM
b000
1
0
1
Normal memory, Shareable, write-through
External SRAM
b000
1
Normal memory, Shareable, write-back, write-allocate
Peripherals
b000
0
1
Device memory, Shareable
In the EFM32 devices the shareability and cache policy attributes do not affect the system behavior.
However, using these settings for the MPU regions can make the application code more portable and
also be useful for setups with the DMA Controller. The values given are for typical situations.