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參數(shù)資料
| 型號： | EFM32-TG222F32-SK |
| 廠商： | Energy Micro |
| 文件頁數(shù)： | 46/136頁 |
| 文件大小： | 0K |
| 描述： | IC MICRO KIT GECKO 48LQFP |
| 標準包裝： | 1 |
| 系列： | Tiny Gecko |
| 套件類型： | 微控制器 |
| 值： | 2 件 - 閃存 - 32KB |
| 包裝： | 紙板盒 |
| 安裝類型： | 表面貼裝 |
| 包括封裝： | 48-LQFP |
| 其它名稱： | 914-1021 |
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...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
17
www.energymicro.com
Address
range
Memory region
Memory
type
XN
Description
0x60000000
-
0x9FFFFFFF
External RAM
Normal
1
-
Executable region for data.
0xA0000000
-
0xDFFFFFFF
External device
Device
1
XN
1
External Device memory
0xE0000000
-
0xE00FFFFF
Private
Peripheral Bus
Strongly-
ordered
1
XN
1
This region includes the NVIC, System timer, and system control
block.
0xE0100000
-
0xFFFFFFFF
Reserved
Device
1
XN
1
Reserved
1See Section 2.2.1 (p. 15) for more information.
The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends that
programs always use the Code region. This is because the processor has separate buses that enable
instruction fetches and data accesses to occur simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see Section 4.5 (p. 113) .
2.2.4 Software ordering of memory accesses
The order of instructions in the program flow does not always guarantee the order of the corresponding
memory transactions. This is because:
the processor can reorder some memory accesses to improve efficiency, providing this does not affect
the behavior of the instruction sequence.
the processor has multiple bus interfaces
memory or devices in the memory map have different wait states
some memory accesses are buffered or speculative.
Section 2.2.2 (p. 16) describes the cases where the memory system guarantees the order of memory
accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier
instructions to force that ordering. The processor provides the following memory barrier instructions:
DMB
The
Data
Memory
Barrier
(DMB)
instruction
ensures
that
outstanding memory transactions complete before subsequent
memory transactions. See Section 3.10.3 (p. 81) .
DSB
The Data Synchronization Barrier (DSB) instruction ensures that
outstanding memory transactions complete before subsequent
instructions execute. See Section 3.10.4 (p. 82) .
ISB
The Instruction Synchronization Barrier (ISB) ensures that the effect
of all completed memory transactions is recognizable by subsequent
instructions. See Section 3.10.5 (p. 82) .
Use memory barrier instructions in, for example:
MPU programming:
Use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of context
switching.
Use an ISB instruction to ensure the new MPU setting takes effect immediately after programming
the MPU region or regions, if the MPU configuration code was accessed using a branch or call.
If the MPU configuration code is entered using exception mechanisms, then an ISB instruction is
not required.
Vector table. If the program changes an entry in the vector table, and then enables the corresponding
exception, use a DMB instruction between the operations. This ensures that if the exception is taken
immediately after being enabled the processor uses the new exception vector.
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| 7810 0.25MM | ECAP COND PAD .25MM 7.7" X 10" |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| EFM32TG222F32-T | 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 48TQFP |
| EFM32TG222F8 | 功能描述:ARM微控制器 - MCU 8KB Flash 2KB RAM RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| EFM32TG222F8-QFP48 | 制造商:Energy Micro AS 功能描述:TINY GECKO MCU - Tape and Reel 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 8KB FLASH 48TQFP |
| EFM32TG222F8-QFP48T | 制造商:Energy Micro AS 功能描述:32 BIT ARM MPU, TINY GECKO - Trays |
| EFM32TG222F8-QFP48-T | 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 8KB FLASH 48TQFP |
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