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| 型號： | EFM32-TG822F32-SK |
| 廠商： | Energy Micro |
| 文件頁數(shù)： | 20/136頁 |
| 文件大小： | 0K |
| 描述： | IC MICRO KIT GECKO 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Tiny Gecko |
| 套件類型： | 微控制器 |
| 值： | 2 件 - 閃存 - 32KB |
| 包裝： | 紙板盒 |
| 安裝類型： | 表面貼裝 |
| 包括封裝： | 48-LQFP |
| 其它名稱： | 914-1023 |
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...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
116
www.energymicro.com
Bits
Name
Function
0 = MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value
of the ENABLE bit
1 = the MPU is enabled during hard fault, NMI, and FAULTMASK handlers.
When the MPU is disabled, if this bit is set to 1 the behavior is Unpredictable.
[0]
ENABLE
Enables the MPU:
0 = MPU disabled
1 = MPU enabled.
When ENABLE and PRIVDEFENA are both set to 1:
For privileged accesses, the default memory map is as described in Section 2.2 (p. 14) . Any access
by privileged software that does not address an enabled memory region behaves as defined by the
default memory map.
Any access by unprivileged software that does not address an enabled memory region causes a
memory management fault.
XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of
the ENABLE bit.
When the ENABLE bit is set to 1, at least one region of the memory map must be enabled for the system
to function unless the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is set to 1 and no regions
are enabled, then only privileged software can operate.
When the ENABLE bit is set to 0, the system uses the default memory map. This has the same memory
attributes as if the MPU is not implemented, see Table 2.11 (p. 16) . The default memory map applies
to accesses from both privileged and unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are always permitted.
Other areas are accessible based on regions and whether PRIVDEFENA is set to 1.
Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing the handler for
an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or NMI
exception, or when FAULTMASK is enabled. Setting the HFNMIENA bit to 1 enables the MPU when
operating with these two priorities.
4.5.3 MPU Region Number Register
The RNR selects which memory region is referenced by the RBAR and RASR registers. See the register
summary in Table 4.38 (p. 114) for its attributes. The bit assignments are:
Reserved
31
8 7
0
REGION
Table 4.41. RNR bit assignments
Bits
Name
Function
[31:8]
-
Reserved.
[7:0]
REGION
Indicates the MPU region referenced by the RBAR and RASR registers.
The MPU supports 8 memory regions, so the permitted values of this field are 0-7.
Normally, you write the required region number to this register before accessing the RBAR or RASR.
However you can change the region number by writing to the RBAR with the VALID bit set to 1, see
Section 4.5.4 (p. 117) . This write updates the value of the REGION field.
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