Notes to tables: (1) See the Operating Requirements for " />

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參數資料
型號： EPF10K70RC240-4
廠商： Altera
文件頁數： 73/128頁
文件大小： 0K
描述： IC FLEX 10K FPGA 70K 240-RQFP
產品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
產品變化通告： Package Change 30/Jun/2010
標準包裝： 24
系列： FLEX-10K®
LAB/CLB數： 468
邏輯元件/單元數： 3744
RAM 位總計： 18432
輸入/輸出數： 189
門數： 118000
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 240-BFQFP 裸露焊盤
供應商設備封裝： 240-RQFP（32x32）
其它名稱： 544-2244
Altera Corporation
49
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
(2)
Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.75 V
for input currents less than 100 mA and periods shorter than 20 ns.
(3)
Numbers in parentheses are for industrial-temperature-range devices.
(4)
Maximum VCC rise time is 100 ms. VCC must rise monotonically.
(5)
EPF10K50V and EPF10K130V device inputs may be driven before VCCINT and VCCIO are powered.
(6)
Typical values are for T A = 25° C and VCC = 3.3 V.
(7)
These values are specified under the EPF10K50V and EPF10K130V device Recommended Operating Conditions in
(8)
The IOH parameter refers to high-level TTL or CMOS output current.
(9)
The IOL parameter refers to low-level TTL or CMOS output current. This parameter applies to open-drain pins as
well as output pins.
(10) This value is specified for normal device operation. The value may vary during power-up.
(11) This parameter applies to -1 speed grade EPF10K50V devices, -2 speed grade EPF10K50V industrial temperature
devices, and -2 speed grade EPF10K130V devices.
(12) Capacitance is sample-tested only.
Table 24. EPF10K50V & EPF10K130V Device DC Operating Conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
High-level input voltage
2.0
5.75
V
VIL
Low-level input voltage
–0.5
0.8
V
VOH
3.3-V high-level TTL output
voltage
I OH = –8 mA DC (8)
2.4
V
3.3-V high-level CMOS output
voltage
I OH = –0.1 mA DC (8)
VCCIO – 0.2
V
VOL
3.3-V low-level TTL output
voltage
I OL = 8 mA DC (9)
0.45
V
3.3-V low-level CMOS output
voltage
I OL = 0.1 mA DC (9)
0.2
V
II
Input pin leakage current
VI = 5.3 V to –0.3 V (10)
–10
10
A
IOZ
Tri-stated I/O pin leakage
current
VO = 5.3 V to –0.3 V (10)
–10
10
A
ICC0
VCC supply current (standby)
VI = ground, no load
0.3
10
mA
VI = ground, no load (11)
10
mA
Table 25. EPF10K50V & EPF10K130V Device Capacitance
Symbol
Parameter
Conditions
Min
Max
Unit
CIN
Input capacitance
VIN = 0 V, f = 1.0 MHz
10
pF
CINCLK Input capacitance on dedicated
clock pin
VIN = 0 V, f = 1.0 MHz
15
pF
COUT
Output capacitance
VOUT = 0 V, f = 1.0 MHz
10
pF
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