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參數資料
| 型號： | FAN5068DDR |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | FAN5068 Component calculation and simulation tools |
| 中文描述： | FAN5068組件的計算和模擬工具 |
| 文件頁數： | 12/18頁 |
| 文件大?。?/td> | 159K |
| 代理商： | FAN5068DDR |
PRODUCT SPECIFICATION
FAN5068
12
REV. 1.0.1 9/9/04
Figure 9. Improving Current Sensing Accuracy
More accurate sensing can be achieved by using a resistor
(R1) instead of the R
DS(ON)
of the FET as shown in Figure 9.
This approach causes higher losses, but yields greater accu-
racy. R1 is a low value (e.g. 10m
) resistor.
Current limit (I
LIMIT
) should be set sufficiently high as to
allow inductor current to rise in response to an output load
transient. Typically, a factor of 1.3 is sufficient. In addition,
since I
LIMIT
is a peak current cut-off value, we will need to
multiply I
LOAD(MAX)
by the inductor ripple current (we'll
use 20%).
I
LIMIT
> I
LOAD(MAX)
* 1.6 * 1.3 * 1.2
(8)
Gate Driver Section
The Adaptive gate control logic translates the internal PWM
control signal into the MOSFET gate drive signals providing
necessary amplification, level shifting and shoot-through
protection. Also, it has functions that help optimize the IC
performance over a wide range of operating conditions.
Since MOSFET switching time can vary dramatically from
type to type and with the input voltage, the gate control logic
provides adaptive dead time by monitoring the gate-to-
source voltages of both upper and lower MOSFETs. The
lower MOSFET drive is not turned on until the gate-to-
source voltage of the upper MOSFET has decreased to less
than approximately 1 volt. Similarly, the upper MOSFET is
not turned on until the gate-to-source voltage of the lower
MOSFET has decreased to less than approximately 1 volt.
This allows a wide variety of upper and lower MOSFETs to
be used without a concern for simultaneous conduction, or
shoot-through.
There must be a low-resistance, low-inductance path
between the driver pin and the MOSFET gate for the adap-
tive dead-time circuit to work properly. Any delay along that
path will subtract from the delay generated by the adaptive
dead-time circit and shoot-through may occur.
Frequency Loop Compensation
The loop is compensated using a feedback network around
the error amplifier, which is a voltage output op amp.
Figure 10. Compensation Network
Figure 10 shows a complete type 3 compensation network. A
type 2 compensation configuration eliminates R4 and C3 and
is shown in Figure 1. Since the FAN5068 architecture
employs summing current mode, type 2 compensation can
be used for most applications. For critical applications that
require wide loop-bandwidth, and use very low ESR output
capacitors, type 3 compensation may be required. The
PSPICE model and spreadsheet calculator can be used to cal-
culate these component values.
PGOOD Signal
PGOOD monitors the status of the PWM output as well as
the VTT and 1.2V LDO regulators. PGOOD remains low
unless all of the conditions below are met:
1.
S3#I is HIGH
2.
SS is above 4V
3.
Fault latch is cleared
4.
FB is between 90% and 110% of VREF
5.
VTT and LDO 1.2 are in regulation
Protection
The converter output is monitored and protected against
extreme overload, short circuit, over-voltage and under-volt-
age conditions.
An internal “Fault Latch” is set for any fault intended to shut
down the IC. When the “Fault Latch” is set, the IC will dis-
charge VOUT by driving LDRV high until VDDQ IN < 0.5V.
LDRV will then go low until VDDQ IN > 0.8V. This behav-
ior will discharge the output without causing undershoot
(negative output voltage).
To discharge the output capacitors, a 50
load resistor is
switched in from VDDQ IN to PGND whenever the IC is in
fault condition, or when EN is low. After a latched fault,
operation can be restored by recycling power or by toggling
the EN pin.
Under-Voltage Shutdown
If FB stays below the under-voltage threshold for 2μs, the
“Fault latch” is set. This fault is prevented from setting the
fault latch during PWM soft-start (SS < 1.3V).
LDRV
PGND
ISNS
R
SENSE
R1
Q2
R4
VREF
VDDQ
FB
COMP
R3
R2
R1
C3
C1
C2
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