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參數資料
| 型號： | FM8P56E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | EPROM/ROM-Based 8-Bit Microcontroller Series |
| 中文描述： | 存儲器/基于ROM的8位微控制器系列 |
| 文件頁數： | 13/50頁 |
| 文件大小： | 368K |
| 代理商： | FM8P56E |
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FM8P54/56
Rev1.21 May 31, 2005
P.13/FM8P54/56
FEELING
TECHNOLOGY
/PHB7
: = 0, Enable the internal pull-high of IOB7 pin.
= 1, Disable the internal pull-high of IOB7 pin.
2.1.13 INTEN (Interrupt Mask Register)
Address
Name
0Eh (r/w)
INTEN
T0IE
: Timer0 overflow interrupt enable bit.
= 0, Disable the Timer0 overflow interrupt.
= 1, Enable the Timer0 overflow interrupt.
PBIE
: Port B input change interrupt enable bit.
= 0, Disable the Port B input change interrupt.
= 1, Enable the Port B input change interrupt .
INTIE
: External INT pin interrupt enable bit.
= 0, Disable the External INT pin interrupt.
= 1, Enable the External INT pin interrupt.
Bit6:BIT3
: Not used. Read as “0”s.
GIE
: Global interrupt enable bit.
= 0, Disable all interrupts. For wake-up from SLEEP mode through an interrupt event, the device will continue
execution at the instruction after the SLEEP instruction.
= 1, Enable all un-masked interrupts. For wake-up from SLEEP mode through an interrupt event, the device
will branch to the interrupt address (008h).
Note : When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the
GIE bit will be cleared by hardware to disable any further interrupts. The RETFIE instruction will exit the
interrupt routine and set the GIE bit to re-enable interrupt.
2.1.14 INTFLAG (Interrupt Status Register)
Address
Name
B7
B6
B5
0Fh (r/w)
INTFLAG
-
-
-
T0IF
: Timer0 overflow interrupt flag. Set when Timer0 overflows, reset by software.
PBIF
: Port B input change interrupt flag. Set when Port B input changes, reset by software.
INTIF
: External INT pin interrupt flag. Set by rising/falling (selected by INTEDG bit (OPTION<6>)) edge on INT pin,
reset by software.
Bit7:BIT3
: Not used. Read as “0”s.
2.1.15 ACC (Accumulator)
Address
Name
B7
B6
B5
N/A (r/w)
ACC
Accumulator is an internal data transfer, or instruction operand holding. It can not be addressed.
B7
GIE
B6
-
B5
-
B4
-
B3
-
B2
INTIE
B1
PBIE
B0
T0IE
B4
-
B3
-
B2
INTIF
B1
PBIF
B0
T0IF
B4
Accumulator
B3
B2
B1
B0
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