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參數資料
| 型號： | FM8P56E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | EPROM/ROM-Based 8-Bit Microcontroller Series |
| 中文描述： | 存儲器/基于ROM的8位微控制器系列 |
| 文件頁數： | 9/50頁 |
| 文件大小： | 368K |
| 代理商： | FM8P56E |
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FM8P54/56
Rev1.21 May 31, 2005
P.9/FM8P54/56
FEELING
TECHNOLOGY
2.1.4 STATUS (Status Register)
Address
03h (r/w)
STATUS
This register contains the arithmetic status of the ALU, the RESET status.
If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these
three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO
are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different
than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves the
STATUS Register as 000u u1uu (where u = unchanged).
C
: Carry/borrow bit.
ADDAR, ADDIA
= 1, a carry occurred.
= 0, a carry did not occur.
SUBAR, SUBIA
= 1, a borrow did not occur.
= 0, a borrow occurred.
Note : A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR, RLR)
instructions, this bit is loaded with either the high or low order bit of the source register.
DC
: Half carry/half borrow bit.
ADDAR, ADDIA
= 1, a carry from the 4th low order bit of the result occurred.
= 0, a carry from the 4th low order bit of the result did not occur.
SUBAR, SUBIA
= 1, a borrow from the 4th low order bit of the result did not occur.
= 0, a borrow from the 4th low order bit of the result occurred.
Z
:
Zero bit.
= 1, the result of a logic operation is zero.
= 0, the result of a logic operation is not zero.
PD
: Power down flag bit.
= 1, after power-up or by the CLRWDT instruction.
= 0, by the SLEEP instruction.
TO
: Time overflow flag bit.
= 1, after power-up or by the CLRWDT or SLEEP instruction.
= 0, a watch-dog time overflow occurred.
GP2:GP0
: General purpose read/write bits.
2.1.5 FSR (Indirect Data Memory Address Pointer)
Address
Name
B7
B6
B5
04h (r/w)
FSR
*
*
Bit5:Bit0
: Select registers address in the indirect addressing mode. See 2.1.1 for detail description.
Bit7:Bit6
: Not used. Read as “1”s.
Name
B7
GP2
B6
GP1
B5
GP0
B4
TO
B3
PD
B2
Z
B1
DC
B0
C
PD
and
bits
B4
Indirect data memory address pointer
B3
B2
B1
B0
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