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參數資料
| 型號： | FM8P56E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | EPROM/ROM-Based 8-Bit Microcontroller Series |
| 中文描述： | 存儲器/基于ROM的8位微控制器系列 |
| 文件頁數： | 20/50頁 |
| 文件大小： | 368K |
| 代理商： | FM8P56E |
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FM8P54/56
Rev1.21 May 31, 2005
P.20/FM8P54/56
FEELING
TECHNOLOGY
2.6.1 Power-up Reset Timer(PWRT)
The Power-up Reset Timer provides a nominal 18ms delay after Power-on Reset (POR), Brown-out Reset (BOR),
RSTB Reset or WDT time-out Reset. The device is kept in reset state as long as the PWRT is active.
The PWDT delay will vary from device to device due to Vdd, temperature, and process variation.
2.6.2 Oscillator Start-up Timer(OST)
The OST timer provides a 128 oscillator cycle delay (from OSCI input) after the PWRT delay (18ms) is over. This
delay ensures that the X’tal oscillator or resonator has started and stabilized. The device is kept in reset state as
long as the OST is active.
This counter only starts incrementing after the amplitude of the OSCI signal reaches the oscillator input thresholds.
2.6.3 Reset Sequence
When Power-on Reset (POR), Brown-out Reset (BOR), RSTB Reset or WDT time-out Reset is detected, the reset
sequence is as follows:
1. The reset latch is set and the PWRT & OST are cleared.
2. When the internal POR, BOR, RSTB Reset or WDT time-out Reset pulse is finished, then the PWRT begins
counting.
3. After the PWRT time-out, the OST is activated.
4. And after the OST delay is over, the reset latch will be cleared and thus end the on-chip reset signal.
The totally system reset delay time is 18ms plus 128 oscillator cycle time.
FIGURE 2.5: Simplified Block Diagram of on-chip Reset Circuit
WDT
Time-out
WDT
Module
Low Voltage
Detector
(LVD)
Vdd
On-Chip
RC OSC
S Q
Reset
Latch
R Q
RESET
CHIP
POR
RESET
Power-up
Reset Timer
(PWRT)
RESET
Oscillator
Start-up Timer
(OST)
OSCI
Power-on
Reset
(POR)
BOR
RSTB
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