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參數(shù)資料
| 型號(hào)： | FM8P56E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | EPROM/ROM-Based 8-Bit Microcontroller Series |
| 中文描述： | 存儲(chǔ)器/基于ROM的8位微控制器系列 |
| 文件頁(yè)數(shù)： | 7/50頁(yè) |
| 文件大小： | 368K |
| 代理商： | FM8P56E |
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FM8P54/56
Rev1.21 May 31, 2005
P.7/FM8P54/56
FEELING
TECHNOLOGY
2.1.2 TMR0 (Time Clock/Counter register)
Address
Name
01h (r/w)
TMR0
The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the instruction cycle clock or by an
external clock source (T0CKI pin) defined by T0CS bit (OPTION<5>). If T0CKI pin is selected, the Timer0 is
increased by T0CKI signal rising/falling edge (selected by T0SE bit (OPTION<4>)).
The prescaler is assigned to Timer0 by clearing the PSA bit (OPTION<3>). In this case, the prescaler will be cleared
when TMR0 register is written with a value.
2.1.3 PCL (Low Bytes of Program Counter) & Stack
Address
Name
B7
B6
B5
02h (r/w)
PCL
FM8P54/56 devices have a 9-bit (for FM8P54/54E) or 10-bit (for FM8P56/56E) wide Program Counter (PC) and
five-level deep 9-bit (or 10-bit) hardware push/pop stack. The low byte of PC is called the PCL register. This register
is readable and writable. The high byte of PC is called the PCH register. This register contains the PC<9:8> bits and
is not directly readable or writable. All updates to the PCH register go through the PCHBUF register. As a program
instruction is executed, the Program Counter will contain the address of the next program instruction to be executed.
The PC value is increased by one, every instruction cycle, unless an instruction changes the PC.
For a GOTO instruction, the PC<9:0> is provided by the GOTO instruction word. The PCL register is mapped to
PC<7:0>, and the PCHBUF register is not updated.
For a CALL instruction, the PC<9:0> is provided by the CALL instruction word. The next PC will be loaded (PUSHed)
onto the top of STACK. The PCL register is mapped to PC<7:0>, and the PCHBUF register is not updated.
For a RETIA, RETFIE, or RETURN instruction, the PC are updated (POPed) from the top of STACK. The PCL
register is mapped to PC<7:0>, and the PCHBUF register is not updated.
For any instruction where the PCL is the destination, the PC<7:0> is provided by the instruction word or ALU result.
However, the PC<9:8> will come from the PCHBUF<1:0> bits (PCHBUF
PCH).
PCHBUF register is never updated with the contents of PCH.
B7
B6
B5
B4
B3
B2
B1
B0
8-bit real-time clock/counter
B4
B3
B2
B1
B0
Low order 8 bits of PC
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