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參數(shù)資料
| 型號(hào)： | FS6131-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Programmable Line Lock Clock Generator IC |
| 中文描述： | 可編程線鎖定時(shí)鐘發(fā)生器IC |
| 文件頁(yè)數(shù)： | 36/39頁(yè) |
| 文件大小： | 435K |
| 代理商： | FS6131-01 |
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36
FS6131-01
Programmable Line Lock Clock Generator IC
14.0 Device Application: Genlocking
Genlocking refers to the process of synchronizing the
horizontal sync pulses (HSYNC) of a target graphics
system to the HSYNC of a source graphics system. In a
genlocked mode, the FS6131 increases (or decreases)
the frequency of the VCO until the FBK input is frequency
matched and phase-aligned to the frequency applied to
the REF input. Since the feedback divider is within the
graphics system and the graphics system is the source of
the signal applied to the FBK input of the FS6131, the
graphics system is effectively synchronized to the REF
input as shown in Figure 32.
To configure the FS6131 for genlocking, the REF input
(pin 12) and the FBK input (pin 13) are switched directly
onto the feedback input of the PFD. The Reference and
Feedback dividers are not used.
The output clock frequency is:
f
CLK
The only remaining task is to select a Post Divider
modulus (N
Px
) that allows the VCO frequency to be within
its nominal range.
total
horizontal
f
HSYNC
×
=
14.1
A Visual BASIC program is available to completely pro-
gram the FS6131 based on the given parameters.
The FS6131 is being used to genlock an LCD projection
panel system to a VGA card-generated HSYNC. The total
number of pixel clocks generated by the VGA card,
known as the horizontal total, are 800. Therefore, the
LCD panel graphics system that is clocked by the
FS6131 is set to divide the output clock frequency (f
CLK
)
by 800. The input HSYNC reference frequency (f
HSYNC
) is
15kHz.
Example Calculation
Figure 32: Block Diagram: Genlocking
Video Graphics System
System HSYNC
Clock In
Reference
HSYNC
FS6131
VCXO
Divider
(optional)
(optional)
CRYSTAL LOOP
MAIN LOOP
VCXO
XOUT
XIN
Control
ROM
XTUNE
(optional)
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
Charge
Pump
DOWN
UP
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
DOWN
UP
Feedback
Divider
(N
F
)
Internal
Loop
Filter
R
LF
C
LF
EXTLF
I
2
C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0],
POST2[1:0],
POST1[1:0]
REFDIV[11:0]
FBKDIV[14:0]
FBKDSRC[1:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
CLKN
(f
CLK
)
(f
VCO
)
R
IPRG
LOCK/
IPRG
(optional)
Post
Divider
(N
Px
)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
STAT[1:0]
OM[1:0]
Clock
Gobbler
GBL
CMOS/PECL
Output
(f
CLK
)
CLKP
C
LP
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FS6131-01G | 制造商:ONSEMI 制造商全稱(chēng):ON Semiconductor 功能描述:Programmable Line Lock Clock Generator IC |
| FS6131-01G-XTD | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01G-XTP | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTD | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK (IND) RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTP | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK IND RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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