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參數資料
| 型號： | FS6131-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Programmable Line Lock Clock Generator IC |
| 中文描述： | 可編程線鎖定時鐘發生器IC |
| 文件頁數： | 38/39頁 |
| 文件大小： | 435K |
| 代理商： | FS6131-01 |
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38
FS6131-01
Programmable Line Lock Clock Generator IC
15.0 Device Application:
Telecom Clock Regenerator
The FS6131 can be used as a clock regenerator as
shown in Figure 33. This mode uses the voltage-
controlled crystal oscillator (VCXO) in its own phase-
locked loop, referred to as the Crystal Loop. The VCXO
provides a "de-jittered" multiple of the reference fre-
quency at the REF pin (usually 8kHz in telecom applica-
tions) for use by the Main Loop. In essence, the Crystal
Loop “cleans up” the reference signal for the Main Loop.
The Control ROM for the VCXO Divider is preloaded with
the most common ratios to permit locking of most stan-
dard telecommunications crystals to an 8kHz signal ap-
plied to the REF pin. The de-jittered multiple of the refer-
ence frequency from the VCXO is then supplied to the
Reference Divider in the Main Loop. The Reference Di-
vider, along with the Feedback Divider, can be pro-
grammed to achieve the desired output clock frequency.
15.1
A Visual BASIC program is available to completely pro-
gram the FS6131 based on the given parameters.
In this example, an 8kHz reference frequency is supplied
to the FS6131 and an output clock frequency of
51.84MHz is desired.
First, select the frequency at which the VCXO will operate
from Table 10. The table shows the external crystal fre-
quency options available to choose from, since the VCXO
runs at the crystal frequency. While the Main Loop can be
programmed to work with any of the frequencies in the
table, the best performance will be achieved with the
highest frequency at the Main Loop PFD.
The frequency at the Main Loop PFD (f
MLpfd
) is the VCXO
frequency (f
VCXO
) divided by the Main Loop Reference
Divider (N
R
).
Example Calculation
R
VCXO
N
MLpfd
f
f
=
Figure 33: Block Diagram: Telecom Clock Regenerator
8kHz IN
(typical)
FS6131
VCXO
Divider
(optional)
(optional)
CRYSTAL LOOP
MAIN LOOP
VCXO
XOUT
XIN
Control
ROM
XTUNE
(optional)
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
Charge
Pump
DOWN
UP
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
DOWN
UP
Feedback
Divider
(N
F
)
Internal
Loop
Filter
EXTLF
I
2
C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0],
POST2[1:0],
POST1[1:0]
REFDIV[11:0]
FBKDIV[14:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
(f
REF
)
(f
VCO
)
LOCK/
IPRG
(optional)
Post
Divider
(N
Px
)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
STAT[1:0]
OM[1:0]
Clock
Gobbler
GBL
CMOS/PECL
Output
CLKN
(f
CLK
)
CLKP
FBKDSRC[1:0]
R
LF
C
LF
R
IPRG
C
LP
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相關代理商/技術參數 |
參數描述 |
|---|---|
| FS6131-01G | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Programmable Line Lock Clock Generator IC |
| FS6131-01G-XTD | 功能描述:時鐘發生器及支持產品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01G-XTP | 功能描述:時鐘發生器及支持產品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTD | 功能描述:時鐘發生器及支持產品 I2C PROG PLL CLK (IND) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTP | 功能描述:時鐘發生器及支持產品 I2C PROG PLL CLK IND RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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