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參數資料
| 型號： | FS6131-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Programmable Line Lock Clock Generator IC |
| 中文描述： | 可編程線鎖定時鐘發生器IC |
| 文件頁數： | 5/39頁 |
| 文件大小： | 435K |
| 代理商： | FS6131-01 |
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5
FS6131-01
Programmable Line Lock Clock Generator IC
To enter this mode, set STAT[1] to one and clear
STAT[0] to zero. If the CMOS bit is set to one, the
LOCK/IPRG pin can display the flag. The flag is always
available under software control by reading back the
STAT[1] bit, which will be overwritten by the flag in this
mode.
4.2.4
The Feedback Divider clock can be brought out the
LOCK/IPRG pin independent of the output clock to allow
monitoring of the Feedback Divider clock. To enter this
mode, set both the STAT[1] and STAT[0] bits to one. The
CMOS bit must also be set to one to enable the
LOCK/IPRG pin as an output.
Feedback Divider Monitoring
4.3
For applications where an external loop filter is required,
the following analysis example can be used to determine
loop gain and stability.
The loop gain of a PLL is the product of all of the gains
within the loop.
Establish the basic operating parameters:
Loop Gain Analysis
Set the charge pump current:
A
I
chgpump
μ
10
=
Set the loop filter values:
pF
C
F
C
k
R
LF
220
015
.
15
2
1
=
=
μ
=
Set the VCO gain (VCOSPD):
V
MHz
A
VCO
N
/
230
=
Set the Feedback Divider:
3500
=
F
Set the Reference frequency (at the input to the Phase
Detector:
kHz
f
REF
20
=
The transfer function of the Phase Detector and Charge
Pump combination is (in A/rad):
π
2
chgpump
PD
I
K
=
The transfer function of the loop filter is (in V/A):
+
+
=
1
2
1
1
1
)
(
sC
R
sC
s
K
LF
LF
The VCO transfer function (in rad/s, and accounting for
the phase integration that occurs in the VCO) is:
s
A
s
K
VCO
VCO
1
2
)
(
π
=
The transfer function of the Feedback Divider is:
F
F
N
K
1
=
Finally, the sampling effect that occurs in the Phase De-
tector is accounted for by:
REF
f
s
SAMP
f
s
e
s
K
REF
=
1
)
(
The loop gain of the PLL is:
(
s
K
LOOP
)
(
)
(
)
(
)
s
K
K
s
K
s
K
K
SAMP
F
VCO
LF
PD
=
Figure 8: Loop Gain vs. Frequency
0.01
Frequency (f
i
)
0.1
0.1kHz
1kHz
10kHz
100kHz
1
10
100
A
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相關代理商/技術參數 |
參數描述 |
|---|---|
| FS6131-01G | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Programmable Line Lock Clock Generator IC |
| FS6131-01G-XTD | 功能描述:時鐘發生器及支持產品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01G-XTP | 功能描述:時鐘發生器及支持產品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTD | 功能描述:時鐘發生器及支持產品 I2C PROG PLL CLK (IND) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTP | 功能描述:時鐘發生器及支持產品 I2C PROG PLL CLK IND RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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