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參數資料
| 型號： | GS832418B |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
| 中文描述： | 200萬× 18，100萬× 36，為512k × 72分配36MB的S /雙氰胺同步突發靜態存儲器 |
| 文件頁數： | 32/46頁 |
| 文件大小： | 1149K |
| 代理商： | GS832418B |
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Rev: 1.00 10/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
32/46
2001, Giga Semiconductor, Inc.
Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
SB
2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
JTAG Port Operation
Due to the fact that this device is built from two die, the two JTAG parts are chained together internally. The following describes
the behavior of each die.
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V
DD
. The JTAG output
drivers are powered by V
DDQ
.
CK
ADSP
ADSC
tH
tKH tKL
tKC
tS
ZZ
tZZR
tZZH
tZZS
~
~
~
~
Snooze
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| GS832418B-133 | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
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| GS832418B-150 | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
| GS832436B-200 | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| GS8324Z36B-133 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 10NS/4NS 119FBGA - Trays |
| GS8324Z36B-200I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 7.5NS/3NS 119FBGA - Trays |
| GS8324Z72C200 | 制造商:G.S.I. 功能描述: |
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| GS8342D06BD-500 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
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