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參數資料
| 型號： | HM17CM256 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 顯示驅動器 |
| 英文描述： | 128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC580 |
| 封裝： | 19.75 X 2.39 MM, GOLD BUMP, DIE-580 |
| 文件頁數： | 17/111頁 |
| 文件大小： | 2094K |
| 代理商： | HM17CM256 |
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HM17CM256
- 17 -
(2) DDRAM and internal register access
DDRAM and internal register are accessed by data bus D
0
~D
7
(D
0
~D
15
), chip select pin (CS),
DDRAM / register select pin (RS), read / write control pin (RD) or WR pin.
When CS=“H”, it is in non-selective state and DDRAM and internal register access is impossible.
During access, Set CS=“L”.
Access selection to DDRAM or internal register is controlled by RS input.
TABLE
RS
Data contents
L
Display RAM data
H
Internal command register
Write process starts after address setting and then the data on the 8bit data bus D
0
~D
7
or 16bit
data bus D
0
~D
15
will be written in by CPU. The data is written at the rising edge of WR (80 series) or
falling edge of E (68 series).
Internally, bus holder data is processed to data bus and data are written to bus holder from CPU
until next cycle.
After address setting, data of assigned address are read at the 1st and 3rd clock, which means it
needs dummy read at the 2nd clock.
There are rules at reading data out of display RAM, after address setting, the data of assigned
address is shown directly after the end of the read command, so pay attention that assigned data is
available at 2nd timing step.
In other words, 1 cycle dummy read is needed after address setting and write cycle.
DATA WRITE IN OPERATION
DATA READ OUT OPERATION
caution) When 16 bit mode, do write in and read out by 16 bit not only RAM access but also command
setting.
\]^
_`
]a
b
n
n+2
D
0
~D
15
WR
BUS HOLDER
WR
n
n+1
n+2
n+3
n+4
n+1
n+3
n+4
D
0
~D
7
(D
0
~D
15
)
RD
n
n
n+1
n+2
data read
n+2 address
WR
address set
n
dummy
read
data read
n address
data read
n+1 address
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