
HM17CM256
- 72 -
(34-23) Set read address of internal register
CS
RS
RD
WR
RE
2
RE
1
RE
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
1
1
0
1
0
0
1
1
0
0
RA
3
RA
2
RA
1
RA
0
( reset :{RA
3
, RA
2
, RA
1
, RA
0
}=B
H
)
Before executing the internal register data read command the address of register should be specified
first. For example, when display control (1) is being read out, { RA
3
, RA
2
, RA
1
, RA
0
} = 8
H
should be
specified first.
Because selected register is corresponded with RE flag, please set RE flag first and then read out the
register.
Refer to the command function description and the lists of commands for the address of each register.
(34-24) Internal register data read
CS
RS
RD
WR
RE
2
RE
1
RE
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
1
1
0
0/1
0/1
0/1
*
*
*
*
Internal register data read
* : “Don’t care”
This command is used to read out internal register data. Before executing this command, RE flag and
the address for internal register to read should be set first.
(34-25) Window end X address set
CS
RS
RD
WR
RE
2
RE
1
RE
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
1
1
0
1
0
1
0
0
0
0
EX
3
EX
2
EX
1
EX
0
( reset :{EX
3
~EX
0
}=0
H
, read address :0
H
)
CS
RS
RD
WR
RE
2
RE
1
RE
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
1
1
0
1
0
1
* : “Don’t care”
0
0
0
1
*
EX
6
EX
5
EX
4
( reset :{EX
6
~EX
4
}=0
H
, read address :1
H
)
When the window area of RAM is specified(WIN=“1”) to access, the end X address of the window is set
by this command. The lower 4 bits of address should be set first and then upper 3 bits are set later
(34-26) Window end Y address set
CS
RS
RD
WR
RE
2
RE
1
RE
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
1
1
0
1
0
1
0
0
1
0
EY
3
EY
2
EY
1
EY
0
( reset :{EY
3
~EY
0
}=0
H
, read address :2
H
)
CS
RS
RD
WR
RE
2
RE
1
RE
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
1
1
0
1
0
1
* : “Don’t care”
0
0
1
1
*
EY
6
EY
5
EY
4
( reset :{EY
6
~EY
4
}=0
H
, read address :3
H
)
When window area of RAM is specified(WIN=“1”) to access , the end Y address of the window is set by
this command. The lower 4 bits of address should be set first and then upper 3 bits are set later.