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參數資料
| 型號： | HM6P5331 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | XO, clock |
| 英文描述： | HM6P5331 - 2.0GHz/500MHz Dual Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PBGA24 |
| 封裝： | PLASTIC, LGA-24 |
| 文件頁數： | 5/10頁 |
| 文件大小： | 195K |
| 代理商： | HM6P5331 |
PRELIMINARY
D
O
IF
D
O
RF
f
IN
IF
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!
#$%
f
IN
RF
Functional Description
The simplified block diagram below shows the 22-bit data
register, two 15-bit R Counters and the 15-bit and 18-bit N
Counters (intermediate latches are not shown). The data
stream is clocked (on the rising edge of Clock) into the
DATA input, MSB first. The last two bits are the Control
Bits. The DATA is transferred into the counters as follows:
CONTROL BITS
C1
0
0
1
1
C2
0
1
0
1
DATA LOCATION
IF R Counter
RF R Counter
IF N Counter
RF N Counter
Programmable Reference Dividers (IF and RF R Counters)
If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22bit shift register into a latch which
sets the 15-bit R Counter. Serial data format is shown below.
15-Bit Programmable Reference Divider Ratio (R Counter)
DIVIDE
RATIO
3
4
R
15
0
0
R
14
0
0
R
13
0
0
R
12
0
0
R
11
0
0
R
10
0
0
R
9
0
0
R
8
0
0
R
7
0
0
R
6
0
0
R
5
0
0
R
4
0
0
R
3
0
1
R
2
1
0
R
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
32767
NOTES:
1. Divide ratios less than 3 are prohibited.
2. Divide ratio: 3 to 32767.
3. R1 to R15: These bits select the divide ratio of the programmable reference divider.
4. Data is shifted in MSB first.
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