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參數資料
| 型號： | HM6P5331 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | XO, clock |
| 英文描述： | HM6P5331 - 2.0GHz/500MHz Dual Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PBGA24 |
| 封裝： | PLASTIC, LGA-24 |
| 文件頁數： | 7/10頁 |
| 文件大小： | 195K |
| 代理商： | HM6P5331 |
PRELIMINARY
Programmable Modes
Several modes of operation can be programmed with bits R16-R18 including the phase detector polarity and charge pump
High Z State. The prescaler and powerdown modes are selected with bits N19 and N20. The programmable modes and
truth table for the programmable modes are shown below.
C1
C2
R16
R17
R18
R19
R20
0
0
1
1
0
1
0
1
IF Phase Detector Polarity
RF Phase Detector Polarity
-
-
IF I
CPO
RF I
CPO
-
-
IF D
O
High Z
RF D
O
High Z
-
-
IF LD
RF LD
IF Prescaler
RF Prescaler
IF F
O
RF F
O
Powerdown IF
Powerdown RF
Mode Select Truth Table
PHASE DETECTOR
POLARITY
D
O
High Z STATE
I
CPO
(NOTE 1)
IF PRESCALER
RF
PRESCALER
POWERDOWN
(NOTE 2)
0
1
Negative
Positive
Normal Operation
High Z State
LOW
HIGH
8/9
16/17
64/65
128/129
Powered Up
Powered Down
NOTES:
1. Activation of the IF PLL or RF PLL powerdown modes result in the disabling of the respective N counter divider and
debiasing of its respective f
IN
inputs (to a high impedance state). Powerdown forces the respective charge pump and
phase comparator logic to a High Z State condition. The R counter functionality does not become disabled until both IF
and RF powerdown bits are activated. The OSC
IN
pin reverts to a high impedance state when this condition exists. The
control register remains active and capable of loading and latching in data during all the powerdown modes.
F
O
LD (Pin 10) Output Truth Table
RF R[19]
(RF LD)
IF R[19]
(IF LD)
RF R[20]
(RF F
O
)
0
0
0
0
0
1
0
1
1
1
1
1
IF R[20]
(IF F
O
)
0
0
0
0
1
0
1
0
1
1
1
1
F
O
OUTPUT STATE
0
0
1
1
X
X
X
X
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
Disabled (Note1)
IF Lock Detect (Note2)
RF Lock Detect (Note2)
RF/IF Lock Detect (Note2)
IF Reference Divider Output
RF Reference Divider Output
IF Programmable Divider Output
RF Programmable Divider Output
For Internal Use Only
For Internal Use Only
For Internal Use Only
Counter Reset (Note4)
X = don’t care condition
NOTES:
1. When the F
O
LD output is disabled, it is actively pulled to a low logic state.
2. Lock detect output provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is
selected, the pins output is HIGH, with narrow pulse LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and
IF are both locked.
3. The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits then N counter resumes
counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle). If the Reset bits are activated the R
counter is also forced to Reset, allowing smooth acquisition upon powering up.
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