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參數資料
| 型號： | HMS77C1001A |
| 廠商： | Hynix Semiconductor Inc. |
| 元件分類： | 數學處理器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數： | 20/45頁 |
| 文件大小： | 549K |
| 代理商： | HMS77C1001A |
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HMS77C1000A/HMS77C1001A
Oct. 2001 Ver. 2.0
17
8. ARCHITECTURE
8.1 CPU Architecture
The HMS700 core is a RISC-based CPU and uses a modi-
fied Harvard architecture. This architecture uses two sepa-
rate memories with separate address buses, one for the
program memory and the other for the data memory. This
architecture adapts 33 single word instructions that are 12-
bit wide instruction and has an internal 2-stage pipeline
(fetch and execute), which results in execution of one in-
struction per single cycle(200ns @ 20MHz) except for pro-
gram branches.
The HMS77C100XA can address 1K x 12 Bits program
memory and 25 Bytes data memory. And it can directly or
indirectly address data memory.
The HMS700 core has three special function registers -
PC, STATUS and FSR - in data memory map and has ATU
(Address Translation Unit) to provide address for data
memory and has an 8-bit general purpose ALU and work-
ing register(W) as an accumulator. The W register consists
of 8-bit register and it can not be an addressed register.
FIGURE 8-1 HMS700 CPU BLOCK DIAGRAM
Instruction
Decode
&
Control
Unit
STATUS
FSR
W
ALU
Instruction
Program Memory Address
Immediate Data
Data Bus
Data Memory Bus
Indirect Address
Address Translation
Unit
PC with 2-level Stack
Control
Signals
ALU
Status
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