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參數(shù)資料
型號(hào)： HMS77C1001A
廠商： Hynix Semiconductor Inc.
元件分類： 數(shù)學(xué)處理器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁(yè)數(shù)： 41/45頁(yè)
文件大小： 549K
代理商： HMS77C1001A
HMS77C1000A/HMS77C1001A
38
Oct. 2001 Ver. 2.0
16. Power-Down Mode (SLEEP)
For applications where power consumption is a critical
factor, device provides power down mode with Watchdog
operation. Executing of SLEEP Instruction is entrance to
SLEEP mode. In the SLEEP mode, oscillator is turn off
and system clock is disable and all functions is stop, but all
registers and RAM data is held. The wake-up sources from
SLEEP mode are external RESET pin reset and watchdog
time-overflow reset.
16.1 SLEEP
The Power-Down mode is entered by executing a SLEEP
instruction. If enabled, the Watchdog Timer will be cleared
but keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had be-
fore the SLEEP instruction was executed (driving high,
driving low, or hi-impedance).
It should be noted that a RESET generated by a WDT time-
out does not drive the RESET pin low.
For lowest current consumption while powered down, the
EC0 input should be at V
DD
or V
SS
and the RESET pin
must be at a logic high level
.
FIGURE 16-1 TIMING DIAGRAM OF WAKE-UP FROM SLEEP MODE DUE TO EXTERNAL RESET PIN RESET
FIGURE 16-2 TIMING DIAGRAM OF WAKE-UP FROM SLEEP MODE DUE TO WATCHDOG TIME-OVERFLOW RESET
~
Oscillator
(X
IN
pin)
~
~
~
~
Internal
System Clock
~
Internal
RESET
~
~
~
RESET
Fetch SLEEP
Execute SLEEP
Fetch RESET vector
~
Instruction
T
IRT
~
Oscillator
(X
IN
pin)
~
~
~
~
Internal
System Clock
~
Internal
RESET
~
~
~
WDT
Overflow
Fetch SLEEP
Execute SLEEP
Fetch RESET vector
~
Instruction
T
IRT
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