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參數資料
| 型號： | HMS77C1001A |
| 廠商： | Hynix Semiconductor Inc. |
| 元件分類： | 數學處理器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數： | 39/45頁 |
| 文件大小： | 549K |
| 代理商： | HMS77C1001A |
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HMS77C1000A/HMS77C1001A
36
Oct. 2001 Ver. 2.0
The POR circuit does not produce an internal reset when
V
DD
declines.
14.2 Internal Reset Timer (IRT)
The Internal Reset Timer (IRT) provides a fixed 7 ms nom-
inal time-out on reset. The IRT operates on an internal RC
oscillator. The processor is kept in RESET as long as the
IRT is active. The IRT delay allows VDD to rise above
VDD min., and for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic resonators
require a certain time after power-up to establish a stable
oscillation. The on-chip IRT keeps the device in a RESET
condition for approximately 7 ms after the voltage on the
RESET/V
PP
pin has reached a logic high (V
IH
) level and
POR released. Thus, external RC networks connected to
the RESET input are not required in most cases, allowing
for savings in cost-sensitive and/or space restricted appli-
cations. The Device Reset time delay will vary from chip
to chip due to V
DD
, temperature, and process variation.
The IRT will also be triggered upon a Watchdog Timer
time-out. This is particularly important for applications us-
ing the WDT to wake the HMS77C100XA from SLEEP
mode automatically.
FIGURE 14-5 EXTERNAL POWER-ON RESET
CIRCUIT (FOR SLOW VDD POWER- UP)
RESET
- External Power-On Reset circuit is required only if VDD
power-up is too slow. The diode D helps discharge the
capacitor quickly when VDD powers down.
- R < 40 k
is recommended to make sure that voltage
drop across R does not violate the device electrical specifi-
cation
.
- R1 = 100W to 1 kW will limit any current flowing into
RESET from external capacitor C in the event of RESET
pin breakdown due to Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).
R
R1
D
C
V
DD
V
DD
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