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參數資料
| 型號： | HMS77C1001A |
| 廠商： | Hynix Semiconductor Inc. |
| 元件分類： | 數學處理器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數： | 24/45頁 |
| 文件大小： | 549K |
| 代理商： | HMS77C1001A |
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HMS77C1000A/HMS77C1001A
Oct. 2001 Ver. 2.0
21
program.
9.3.5 STATUS Register
This register contains the arithmetic status of the ALU, the
RESET status, and the page select bit for program memo-
ries larger than 512 words.
The STATUS register can be the destination for any in-
struction, as with any other register. If the STATUS regis-
ter is the destination for an instruction that affects the Z,
DC or C bits, then the write to these three bits is disabled.
These bits are set or cleared according to the device logic.
Furthermore, the TO and PD bits are not writable. There-
fore, the result of an instruction with the STATUS register
as destination may be different than intended.
It is recommended that only instructions that do not affect
status of CPU be used on STATUS register. Care should be
exercised when writing to the STATUS register as the
ALU status bits are updated upon completion of the write
operation, possibly leaving the STATUS register with a re-
sult that is different than intended. In reset state, the STA-
TUS register is initialized with “00011XXX
B
”.
FIGURE 9-7 OPERATION OF 2-LEVEL STACK
PC
STACK LEVEL1
STACK LEVEL2
0
9(8)
return
return
subroutine call
HMS77C1001A(HMS77C1000A)
subroutine call
FIGURE 9-8 STATUS REGISTER
-
PA0
R/W
TO
R
PD
R
Z
R/W
DC
R/W
C
R/W
bit7
bit0
PA0
: Program memory page select bits
0 = page 0 (000h - 1FFh) - HMS77C1000A/
1001A
1 = page 1 (200h - 3FFh) - HMS77C1001A
TO
: Time-overflow bit
1 = After power-up, watchdog clear instruction, or
entering power-down mode
0 = A watchdog timer time-overflow occurred
PD
: Power-down bit
1 = After power-up or by the watchdog clear
instruction
0 = By execution of power-down mode
Z
: Zero bit
1 = The result of an arithmetic or logic operation
is zero
0 = The result of an arithmetic or logic operation
is not zero
DC
: Digit carry/borrow bit
(for addition and subtraction)
addition
1 = A carry from the 4th low order bit of the result
occurred
0 = A carry from the 4th low order bit of the result
did not occur
subtraction
1 = A borrow from the 4th low order bit of the
result did not occur
0 = A borrow from the 4th low order bit of the
result occurred
C
: Carry/borrow bit
(for additon,subtraction and rotation)
addition
1 = A carry occurred
0 = A carry did not occur
subtraction
1 = A borrow did not occur
0 = A borrow occurred
rotation
Load bit with LSB or MSB, respectively
R = Readable bit
W = Writable bit
ADDRESS ; 03
H
RESET VALUE : 0001_1XXX
-
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