
HT48RB8
Rev. 1.30
13
February 10, 2003
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set thatresetsonlythePCandSP,leavingtheothercir-
cuits in their original state. Some registers remain un-
changed during other reset conditions. Most registers
are reset to the initial condition when the reset condi-
tions are met. By examining the PD and TO flags, the
programcandistinguishbetweendifferent chipresets .
TO
PD
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
The functional unit chip reset status are shown below.
PC
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/event Counter
Off
Input/output Ports
Input mode
SP
Points to the top of the stack
Reset circuit
+
(
!
+
2
#
, "
!
!
(
!
6
(
,
Reset configuration
(
6
$
( (
!
Reset timing chart