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參數資料
| 型號： | HT48RB8 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit USB Type OTP MCU |
| 中文描述： | 8位微控制器的USB型檢察官辦公室 |
| 文件頁數： | 21/45頁 |
| 文件大小： | 281K |
| 代理商： | HT48RB8 |
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HT48RB8
Rev. 1.30
21
February 10, 2003
MISC register combines a command and status to control desired endpoint FIFO action and to show the status of
wanted endpoint FIFO. The MISC will be cleared by USB reset signal.
MISC
Bits
R/W
Function
REQ
0
R/W
After setting other status of desired one in the MISC, endpoint FIFO can be re-
questedbysettingthisbitto 1 .Afterjobhasbeendone,thisbithastobeclearedto
0
TX
1
R/W
This bit defines the direction of data transferring between MCU and endpoint FIFO.
When the TX is set to 1 , this means that MCU wants to write data to endpoint
FIFO. After the job has been done, this bit has to be cleared to 0 before terminat-
ing request to represent end of transferring. For reading action, this bit has to be
cleared to 0 to represent that MCU wants to read data from endpoint FIFO and has
to be set to 1 after the job done.
CLEAR
2
R/W Clear the requested endpoint FIFO, even the endpoint FIFO is not ready.
SELP1
SELP0
4
3
R/W
To define which endpoint FIFO is selected, SELP1,SELP0:
00: endpoint FIFO0
01: endpoint FIFO1
10: endpoint FIFO2
11: endpoint FIFO3
SCMD
5
R/W
It is used to show that the data in endpoint FIFO is SETUP command. This bit has to
be cleared by firmware. That is to say, even the MCU is busing, the device will not
miss any SETUP commands from host.
READY
6
R
Read only status bit, this bit is used to indicate that the desired endpoint FIFO is
ready to work.
LEN0
7
R/W
Read only status bit, it is sued to indicate that a 0-sized packet is sent from host to
MCU. This bit should be cleared by firmware.
MCU can communicate with endpoint FIFO by setting the corresponding registers, of which address is listed in the fol-
lowing table. After reading current data, next data will show on after 2 s. using to check endpoint FIFO status and re-
sponse to MSIC register, if read/write action is still going on.
Registers
R/W
Bank
Address
Bit7~Bit0
FIFO0
R/W
1
48H
Data7~Data0
FIFO1
R/W
1
49H
Data7~Data0
FIFO2
R/W
1
4AH
Data7~Data0
FIFO3
R/W
1
4BH
Data7~Data0
There are some timing constrains and usages illustrated here. By setting the MISC register, MCU can perform reading,
writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing
and clearing.
Actions
MiSC Setting Flow and Status
Read FIFO0 sequence
00H
check not ready (01H)
01H
delay 2 s, check 41H
read* from FIFO0 register and
03H
02H
Write FIFO1 sequence
0AH
check not ready (0BH)
0BH
delay 2 s, check 4BH
09H
write* to FIFO1 register and
08H
Check whether FIFO0 can be read or not
00H
01H
delay 2 s, check 41H (ready) or 01H (not ready)
00H
Check whether FIFO1 can be written or not
0AH
0BH
delay2 s,check4BH(ready)or0BH(notready)
0AH
Read 0-sized packet sequence form FIFO0
00H
01H
delay 2 s, check 81H
read once (01H)
03H
02H
Write 0-sized packet sequence to FIFO1
0AH
0BH
delay 2 s, check 0BH
0FH
0DH
08H
Note:
*: There are 2 s existing between 2 reading action or between 2 writing action
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