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參數資料
| 型號： | HTG2190 |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit 1024 Pixel LCD Microcontroller |
| 中文描述： | 8位單片機1024像素LCD |
| 文件頁數： | 24/64頁 |
| 文件大小： | 417K |
| 代理商： | HTG2190 |
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HTG2190
Rev. 1.00
24
June 29, 2001
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS register
If the device operates in a noisy environment,
using the on-chip RC oscillator (WDT OSC) is
strongly recommended, since the HALT will
stop the system clock.
The WDT overflow under normal operation will
initialize a chip reset
TO . Whereas in the HALT mode, the overflow
will initialize a warm reset only the PC and
SP are reset to zero. To clear the contents of the
WDT (including the WDT prescaler ), three
methods are adopted; external reset (a low level
to RES), software instructions, or a HALT in-
struction. The software instruction is
WDT
and execution of the
struction will clear the WDT.
and set the status bit
CLR
in-
CLR WDT
Power down operation
HALT
The HALT mode is initialized by a HALT in-
struction and results in the following.
The system oscillator will turn off but the
WDT oscillator keeps running (if the WDT os-
cillator is selected).
The contents of the on chip RAM and regis-
ters remain unchanged.
WDT and WDT prescaler will be cleared and
recount again.
All I/O ports maintain their original status.
The PD flag is set and the TO flag is cleared.
ThesystemcanleavetheHALTmodebymeans
of an external reset, an interrupt, an external
falling edge signal on port A or a WDT overflow.
An external reset causes a device initialization
and the WDT overflow performs a "warm reset".
ByexaminingtheTOandPDflags,thereasonfor
the chip reset can be determined. The PD flag is
cleared when the system powers-up or executing
the CLR WDT instruction and is set when the
HALT instruction is executed. The TO flag is
set if a WDT time-out occurs, and causes a
wake-upthatonlyresetsthePCandSP.Theoth-
ers maintain their original status.
The port A wake-up and interrupt methods can
be considered as a continuation of normal exe-
cution. Each bit in port A can be independently
selected to wake up the device by a mask op-
tion. Awakening from an I/O port stimulus, the
program will resume execution of the next in-
struction. If awakening from an interrupt, two
sequences may happen. If the related interrupt
is disabled or the interrupt is enabled but the
stack is full, the program will resume execution
at the next instruction. If the interrupt is en-
abledandthestackisnotfull,theregularinter-
rupt response takes place.
Once a wake-up event occurs, it takes 1024 t
SYS
(system clock period) to resume normal opera-
tion. In other words, a dummy cycle period will
be inserted after a wake-up. If the wake-up re-
sultsfromaninterruptacknowledge,theactual
interrupt subroutine will be delayed by one
more cycle. If the wake-up results in next in-
struction execution, this will be executed imme-
diately after a dummy period is finished. If an
interrupt request flag is set to "1" before enter-
ing the HALT mode, the wake-up function of
the related interrupt will be disabled.
To minimize power consumption, all I/O pins
should be carefully managed before entering
the HALT status.
Reset
There are 3 ways in which a reset can occur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
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